I had a few questions about Warnings so I thought I would post a hopefully concise answer here.
Often it is the case that you will be designing hardware in either VHDL, Verilog, or Schematic Capture and when synthesizing that design you will receive a series of warnings.
First, it is always important to read through all messages that the tools provide, as it will both give you a better understanding of the tools as well as what they are doing. This will lead to a better functional understanding of how your design is behaving both in simulation and in live silicon.
