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November 2012

Redirecting Peripherals from MIO to EMIO

 

A great question was posted by maw41 on the forums today: http://zedboard.org/content/onboard-ethernet-fpga

maw41 wanted to know if he could pull the signals for the Ethernet MAC within the Processing System (PS) of the Zynq-7000 AP SoC device, out through the Programmable Logic (PL).  The answer is yes!

I thought I would take this opportunity though to talk about how to move signals from the MIO pins (those that are dedicated to the MIO Bank) to the EMIO pins (those that are available to the PL).

Zynq Pins - Deep Dive

 

How to understand Zynq Pins! WooHoo!

 
A good question came up on the forums today by user atkarapa asking about MIO pins on the Zynq-7000.  So let's take a little bit of time going through what pins map to where, and get familiar with the naming schema that Xilinx uses for it's pins.