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Board Definition file bug

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fletch
Moderator(23)
Board Definition file bug

Be aware that there is a bug in the Board Definition that is embedded in Vivado 2018.1 and 2018.2 for Ultra96 that causes the LPDDR4 to fail at the 1GB mark. We are working on a simple patch now.

 

This does not affect the PetaLinux 2018.2 BSP for Ultra96 that was recently published.

 

Bryan

 

dyessgg
Junior(0)
UART_1 not routed correctly

I think there might be another defect in the Ultra96 preset.xml file in the GIT repository.

The 3-pin UART connector is routed to uart_1 at pins MIO 8..9 in hardware. The preset.xml file shows it at the default location of "MIO 0 .. 1". Line 97 should be changed to "MIO 8 .. 9".

Since MIO 8..9 are used as part of SPI1, SPI 1 will have to be disabled by modifying line 77 to value="0".

Additionally, the BSP settings should be modified to route stdin and stdout to uart_1 instead of uart_0.

dyessgg
Junior(0)
UART_1 (cont)

It's interesting the routing of my Ultra96 board matches the HW User Guide r1 v0.9 (which is what I commented on above). It shows uart_1 connected to MIO8..9.

The schematics shows uart_1 routed to MIO0..1, which matches the preset.xml file in the Avnet Github repository.

Is the schematic out of date or is my hardware out of date?

JFoster
Moderator(77)
Hi Dyessgg,

Hi Dyessgg,

Your hardware is up to date as of now. Looking at table 2 in the HW user guide it shows UART connected to MIO 0 and 1. I am not sure what your refering to by MIO 8 and 9.

--Josh

JFoster
Moderator(77)
Hi Dyessgg,

Hi Dyessgg,

I see what your refering to. This is a mistake, thanks for pointing it out. We will work on correcting it.

--Josh

dyessgg
Junior(0)
Hardware vs Schematica

I think I wrote it in a confusing way.

The schematics (and board XML) show UART_1 routed to MIO0..1.
The Getting Started guide and my hardware has uart_1 connected to MIO_8..9.

JFoster
Moderator(77)
Are you saying, that MIO 8..9

Are you saying, that MIO 8..9 send your UART to J6? Thats not possible as J6 is strictly connected to MIO 0 and 1. The BDF also sets up your board design this way. How did you determine 8..9 went to J6 on your U96? When did you purchase/receive your hardware? Did you buy it through Avnet?

--Josh

dyessgg
Junior(0)
UART_1

I got MIO8..9 from the HW User Guide, rev 1.0, Version 0.9, section 5.7:
"Ultra96 provides one UART. PS UART1 (MIO8, MIO9) is connected to a 3 pin 2mm header (J6)."

When I created a Vivado project using the board defaults of MIO0..1, exported to SDK and then created a project based upon that, J6 would not work.

Apparently, I was a bit hasty in my previous post. My issue with J6 not working stemmed from the BSP using uart_0 as the default instead of uart_1. Looks like I was making more than one change at the same time. Sorry for the confusion.

Two things from this:
1. The HW USer Guide is incorrect when it states uart1 is routed via MIO8..9.
2. The default in Vivado/SDK of using uart_0 instead of uart_1 needs to be overridden.

Greg

JFoster
Moderator(77)
Hi Greg,

Hi Greg,

Thanks for the feedback I understand now!

1. We are currently working on reving this document. This has been updated in the new soon to be posted document. Thanks!

2. Unfortunatly this is somthing we cannot do, This is caused by Uart 0 being enabled in the Hardware Platform (which if I recall correctly is for the bluetooth interface). If you do not need this interface, disable Uart0 in the Hardware platform and SDK should enumerate the UART1 interface as the default selection.

--Josh