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Booting from QSPI flash

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gtSasha's picture
Booting from QSPI flash


I am very new to Xilinx/Linux development and am running into a problem trying to boot PetaLinux from QSPI flash.

I used PetaLinux tools to build uBoot and kernel images and then I create boot.bin file like this:

petalinux-package --boot --force --fsbl zynq_fsbl.elf --fpga pre-build/linux/implementation/download.bit --u-boot --kernel

The line above creates a 14MB BOOT.BIN file with FSBL, FPGA program, uBoot, and linux kernel.

I copied BOOT.BIN and image.ub to SD card and it booted fine.

I then copied BOOT.BIN to QSPI flash of my Zed board:

U-Boot-PetaLinux-2> sf probe 0 0 0 #connect to QSPI flash device
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
U-Boot-PetaLinux-2> mmcinfo && fatload mmc 0 ${netstart} ${boot_img} #connect to mmc and load boot image (BOOT.BIN) from mmc to ram address ${netstart}
Device: zynq_sdhci
Manufacturer ID: 27
OEM: 5048
Name: SD04G
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 3.7 GiB
Bus Width: 4-bit
reading BOOT.BIN
14316288 bytes read in 1224 ms (11.2 MiB/s)
U-Boot-PetaLinux-2> sf erase 0 0xDB0000 #14316288 bytes is 0xDA7300 in hex. Aligned to 64K this gives 0xDB0000
SF: 14352384 bytes @ 0x0 Erased: OK
U-Boot-PetaLinux-2> sf write ${netstart} 0x0 0xDA7300 #write 0xDA7300 (14316288) bytes from ${netstart} to flash starting at 0x0
SF: 14316288 bytes @ 0x0 Written: OK
#Verify that boot image saved correctly
U-Boot-PetaLinux-2> md ${netstart} c #dump 12 words of memory starting at address ${netstart}
01000000: eafffffe eafffffe eafffffe eafffffe ................
01000010: eafffffe eafffffe eafffffe eafffffe ................
01000020: aa995566 584c4e58 00000000 01010000 fU..XNLX........
U-Boot-PetaLinux-2> sf read 0x02000000 0x0 0x100 #read 256 bytes from flash address 0x0 to RAM address 0x02000000
SF: 256 bytes @ 0x0 Read: OK
U-Boot-PetaLinux-2> md 0x02000000 c #dump 12 words from memory address 0x02000000
02000000: eafffffe eafffffe eafffffe eafffffe ................
02000010: eafffffe eafffffe eafffffe eafffffe ................
02000020: aa995566 584c4e58 00000000 01010000 fU..XNLX........

I then power-down the board, change jumper settings to boot from QSPI flash and power the board back on.

The board boots into uBoot, but not into linux kernel. I examined memory using iminfo command and it looks like there is no valid image at ${netstart} address where kernel is supposed to be loaded.

My best guess is that FSBL does not load kernel into RAM for some reason.

Is there a way to configure FSBL or BOOT.BIN to make FSBL load kernel into RAM?

Is there a better/proper way to boot from QSPI?

I examined ZedBoard boot guide but there is not information there on how to create proper BOOT.BIN.

I am hoping to find a way to use petalinux-config and petalinux-package to create QSPI-bootable image.

Thank you.

gtSasha's picture
possible solution

I did figure out one possible solution:

I used "Create Zynq Boot Image" tool from Xilinx SDK to create BOOT.BIN and manually specify load and startup address for image.ub

hockeyman1972's picture
u-boot configuration

Hi Sasha,
The problem is not with the FSBL, but rather with the configuration of u-boot.  You need to change the PetaLinux build to have u-boot load the FIT image from QSPI instead of the default of the SD card.   In your current configuration, you should be able to insert your SD card with the image.ub file on it, boot from QSPI and it will likely work.  That confirms you are simply reading the image from the wrong place.
Have a look at the Booting PicoZed from QSPI and eMMC under the PicoZed reference designs.  In the QSPI booting chapter, it explains the steps you need to follow to get it to work entirely from QSPI.  The material was originally targeted at PicoZed because of the eMMC, but that section is applicable to any Zynq device.

CHITHRA's picture
Boot program from FPGA

I am working with the following
      vivado 2014.4
I written a counter program and generated bit stream and loaded to FPGA directly through J17(PROG) connector with default configuration to JP7 to JP11. 
I want to make my program non volatile. I am very new to vivado and zedboard...
Please help me by suggesting a proper procedure (software and Hardware) 
Please excuse me for this basic question and help me out of this
Thank you... 

JFoster's picture
Hello Chithra,

Hello Chithra,

My suggestions would be for you to download the Devleloping Zynq Software Speedway located here

In lab 6 and 7 it goes over how to put a application/HW platform in nonvolatile memory.