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Changing Voltage on PS SPI when routed to EMIO

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Kalicutt's picture
Kalicutt
Junior(0)
Changing Voltage on PS SPI when routed to EMIO

I am using SPI to talk to another board with the Zynq. In order to go to the right pins, I routed the SPI to the EMIO. I took care of the issue with multi master mode by tying SS_0 high, and made the bank voltage where the SPI were being routed to LVCMOS33. Despite all this, I am not seeing 3.3V logic when looking at the signals on an oscilloscope digital logic probe. The voltage is always 2.5V.

I read it was an issue with the PS-PL voltage level shifters not being enabled, however when adding the recommendations on page 47 of the TRM to the FSBL through the fsbl_hooks.c and making sure the operations and registers were correct, the problem persisted.

I am driving the SPI master using the Cadence SPI driver and sending simple signals. Any help on this matter is greatly appreciated. There was another post with a similar issue but they found the problem to be that their pins were being shorted, https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-SPI-via-EMIO..., which I am confident is not the case here.

TroutChaser's picture
TroutChaser
Moderator(18)
Hello Nelson,

Hello Nelson,
 
Based on the forum this is posted in I will assume you are working with a ZedBoard.
 
You don't say which I/O Banks your signals are assigned to, but Bank 34 and Bank 35 I/O are powered from an adjustable voltage (VADJ) set by Jumper J18. The default is 2.5V due to the fact that 3.3V can damage some FMC cards. If this is your issue take a look at section2.9.1 of the ZedBoard Hardware Users Guide for instructions on setting VADJ to 3.3V:
 
http://picozed.org/support/documentation/1521
 
Or you might be able to move your SPI signals to Bank 13, which is set to 3.3V.
 
If this is not your issue give us a little more information on your tools version, the signals you have assigned, etc.
 
-Gary

Kalicutt's picture
Kalicutt
Junior(0)
Hello Gary,

Hello Gary,

I am working with a Zynq product, not specifically a ZedBoard but I figured it would be a good place to ask since it is a development board for the device. I am constrained to using Bank 34 right now due to physical pin outs of the system, which I have set to 3.3V (LVCMOS33) inside of the Vivado synthesized design (Using Vivado 2014.4 with Zynq 7020).

TroutChaser's picture
TroutChaser
Moderator(18)
Nelson,

Nelson,
 
Did you check to make sure that the VCCIO for Bank 34 is set to 3.3V physically on your board? It does not matter what I/O standard you have set the pin to in the design if the VCCIO does not match. That sounds like your issue to me.
 
-Gary

Kalicutt's picture
Kalicutt
Junior(0)
Yes this is exactly it!

Yes this is exactly it! Thanks so much for the help. Turns out the voltage regulator was not properly programmed for what we want to do.