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DDR3 CKE recommendation

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fletch's picture
DDR3 CKE recommendation

Xilinx has recently changed their recommendation for DDR3 CKE.  ZedBoard Rev C implements a 4.7K-ohm pulldown to GND.  The new recommendation is a 40-ohm pull-up to Vtt.
The Micron spec only requires CKE to be low 10ns before RESET#, unlike DDR2 where the term was longer. Since the Zynq controller drives CKE low, that 10ns requirement is met.  The termination to VTT could be important for self-refresh users, as CKE will toggle more often than just startup. The 4.7K pulldown may lead to poor SI on this potentially high-frequency signal.

TimDuffy's picture


Does this apply for both the PS *and* any PL MIG based DDR3 interface(s)? Or just the PS connection(s)?

fletch's picture
This applies to all DDR3. 

This applies to all DDR3.  MIG is being updated to reflect this even for other 7-series.  If you look at a Micron DIMM, this is how it is done on the DDR3 DIMMs.

ZedBoard's DDR3 Interface

As i understand from ZedBoard Hardware User’s Guide (v1.2) DDR3 is dedicated to PS side only. Additionally as i know ZYNQ doesn't have a limitaion like ZedBoard. 
TimDuffy's question made me confused. 
What i want to ask is: Am i right about the below knowledges?
1. "ZedBoard's DDR3 can only be progrrammed over DMA by ZYNQ processor. ZedBoard has no PL's DDR3 usage over MIG7 IP. "
2. "Zynq doesn't have a limitation like ZedBoard. PL side can have direct DDR3 interface." 

version correction

Version i mentioned was 2.2, not 1.2.  :)

JFoster's picture
Hello Sercan_Egilmezkol,

Hello Sercan_Egilmezkol,

1. That is correct, the Zedboard only has DDR3 memory accessible through the PS. There is no DDR3 memory accessible through the PL using a MIG IP.

2. This is also correct. The Zynq device does not limit the DDR3 memory to being accessed only through the PS. This just happened to be the setup that was chosen for the Zedboard. If you refer to the Mini_ITX hardware user guide you will see that we have DDR3 memory located on both the PS and PL side of the Zynq Device.