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DRAM to DDR issue in Zedboard

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prakhar's picture
prakhar
Junior(3)
DRAM to DDR issue in Zedboard

Hi.
I am facing issue with reading from DDR memory to PL(led's).
i have connected fabric hardware like shown in image on this link https://drive.google.com/folderview?id=0Byl0l4ua8ptEaXJ2SUFibVZJekk&usp=... , address allocated to all hardware are also shown in image.
also i have written following code for configuring hardware

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CODE :
/*
* Copyright (c) 2009-2012 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
*/

/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/

#include <stdio.h>
#include "platform.h"
#include "ps7_init.h"
#include <xil_io.h>
#include "xscugic.h"
#include "xparameters.h"

/********************************Write Data**********************************/
void StartDMATransfer (unsigned int dest_addr , unsigned int length)
{
u32 addr1;
u32 addr2;

addr1 = XPAR_AXI_DMA_0_BASEADDR + 0x48;
addr2 = XPAR_AXI_DMA_0_BASEADDR + 0x58;
//Writing Address to S2MM_DA register
Xil_Out32(addr1 , dest_addr);
//Writing Length to S2MM_LENGTH register
Xil_Out32(addr2 , length);
}
/********************************Read Data**********************************/
void Read_Data (unsigned int dest_addr , unsigned int length)
{
u32 addr1;
u32 addr2;

addr1 = XPAR_AXI_DMA_1_BASEADDR + 0x18;
addr2 = XPAR_AXI_DMA_1_BASEADDR + 0x28;
//Writing Address to MM2S_DA register
Xil_Out32(addr1 , dest_addr);
//Writing Length to MM2S_LENGTH register
Xil_Out32(addr2 , length);
}

/*******************Interrupt_Handler*******************/
XScuGic InterruptController0;
XScuGic InterruptController1;
static XScuGic_Config *GicConfig0;
static XScuGic_Config *GicConfig1;
u32 frame_count0;
u32 frame_count1;

/*************************Write Interrupt***********************/
void InterruptHandler1(void)
{
u32 tmpval;
u32 addr1;

addr1 = XPAR_AXI_DMA_0_BASEADDR + 0x34;
// xil_printf("Interrupt Acknowledgment.\n\r");

// Interrupt clear and write to bit no. 12 of S2MM_DMASR
tmpval = Xil_In32(addr1);
tmpval = tmpval | 0x1000;
Xil_Out32(addr1,tmpval);

//DRAM DATA PROCESSING
frame_count1++;
if(frame_count1 > 10000000)
{
xil_printf("Frame Number write : %d \n\r",frame_count1);
return ;
}

//initiate DATA Transfer
//StartDMATransfer(0xa000000+128*frame_count,256);
StartDMATransfer( 0xa000000, 256);
}

int SetupInterruptSys1(XScuGic *XScuGicInstancePtr1)
{
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler) XScuGic_InterruptHandler,XScuGicInstancePtr1);
Xil_ExceptionEnable();
return XST_SUCCESS;
}

int Initial_Interrupt1(deviceID1)
{
int status;

GicConfig1 = XScuGic_LookupConfig (deviceID1);
if(NULL == GicConfig1 )
{
return XST_FAILURE;
}

status = XScuGic_CfgInitialize (&InterruptController1,GicConfig1,GicConfig1->CpuBaseAddress);
if(status != XST_SUCCESS)
{
return XST_FAILURE;
}

status = SetupInterruptSys1( &InterruptController1 );
if(status != XST_SUCCESS)
{
return XST_FAILURE;
}

status = XScuGic_Connect (&InterruptController1,
XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR,
(Xil_ExceptionHandler)InterruptHandler1,
NULL);
if(status != XST_SUCCESS)
{
return XST_FAILURE;
}

XScuGic_Enable (&InterruptController1 , XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR);

return XST_SUCCESS;
}

/*************************Read Interrupt************************/
void InterruptHandler0(void)
{
u32 tmpval;
u32 addr1;

addr1 = XPAR_AXI_DMA_1_BASEADDR + 0x04;
// xil_printf("Interrupt Acknowledgment.\n\r");

// Interrupt clear and write to bit no. 12 of S2MM_DMASR
tmpval = Xil_In32(addr1);
tmpval = tmpval | 0x1000;
Xil_Out32(addr1,tmpval);

//DRAM DATA PROCESSING
frame_count0++;
if(frame_count0 > 10000000)
{
xil_printf("Frame Number Read: %d \n\r",frame_count0);
return ;
}

//initiate DATA Transfer
//StartDMATransfer(0xa000000+128*frame_count,256);
Read_Data(0xa00000c, 256);
}
int SetupInterruptSys0(XScuGic *XScuGicInstancePtr0)
{
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler) XScuGic_InterruptHandler,XScuGicInstancePtr0);
Xil_ExceptionEnable();
return XST_SUCCESS;
}

int Initial_Interrupt0(deviceID0)
{
int status;

GicConfig0 = XScuGic_LookupConfig (deviceID0);
if(NULL == GicConfig0 )
{
return XST_FAILURE;
}

status = XScuGic_CfgInitialize (&InterruptController0,GicConfig0,GicConfig0->CpuBaseAddress);
if(status != XST_SUCCESS)
{
return XST_FAILURE;
}

status = SetupInterruptSys0( &InterruptController0 );
if(status != XST_SUCCESS)
{
return XST_FAILURE;
}

status = XScuGic_Connect (&InterruptController0,
XPAR_FABRIC_AXI_DMA_1_MM2S_INTROUT_INTR,
(Xil_ExceptionHandler)InterruptHandler0,
NULL);
if(status != XST_SUCCESS)
{
return XST_FAILURE;
}

XScuGic_Enable (&InterruptController0 , XPAR_FABRIC_AXI_DMA_1_MM2S_INTROUT_INTR);

return XST_SUCCESS;
}

/********************************Initialize DMA**********************************/
int Initial_AXI_DMA(void)
{
unsigned int tmp0;
unsigned int tmp1;

u32 addr1;
u32 addr2;

addr2 = XPAR_AXI_DMA_1_BASEADDR + 0x00;
addr1 = XPAR_AXI_DMA_0_BASEADDR + 0x30;
// setting S2MM DMACR.RS = 1
tmp0 = Xil_In32(addr1); // read from address 0x40400000 + 0x30
tmp0 = tmp0 | 0x1001; // Modifying value // enable data unit & interrupt when done
Xil_Out32(addr1,tmp0); // writing back to the same address 0x40400000 + 0x30
tmp0 = Xil_In32(addr1);
xil_printf("DMA S2MM Control Register Value is %x \n\r",tmp0);

// setting MM2S DMACR.RS = 1
tmp1 = Xil_In32(addr2); // read from address 0x40400000 + 0x30
tmp1 = tmp1 | 0x1001; // Modifying value // enable data unit & interrupt when done
Xil_Out32(addr2,tmp1); // writing back to the same address 0x40400000 + 0x30
tmp1 = Xil_In32(addr2);
xil_printf("DMA MM2S Control Register Value is %x \n\r",tmp1);

return 0;
}
/*******************My_ip*******************************/
int Initial_My_IP(unsigned int size)
{
Xil_Out32(XPAR_AXI_GPIO_0_BASEADDR, size); // set Frame Size
Xil_Out32(XPAR_AXI_GPIO_1_BASEADDR, 1); // Enable to generate Samples

return 0;
}
/*****************************MAIN***************************/
int main()
{
init_platform();

ps7_post_config();

char c;

unsigned int d;

xil_printf("Initializing AXI_DMA\n\r"); // Initializing DMA
Initial_AXI_DMA();

xil_printf("Do You Want To Perform Write.....? \n\r");
xil_printf("y for Yes or n for No \n\r");
c= getchar();

if(c=='w')
{
xil_printf("Enabling My_ip to Generate Samples ............\n\r"); // Initializing My_IP
Initial_My_IP(64); // End of frame after 128 Bytes (32 words) transferred

xil_printf("Enabling Write Interrupt Handler ...........\n\r"); // Initializing Interrupts
Initial_Interrupt1(XPAR_PS7_SCUGIC_0_DEVICE_ID);

xil_printf("Writing Begins...........\n\r"); // Initial DMA Transfer
StartDMATransfer( 0xa000000, 256);
c = 'a';
}
else if(c=='r')
{
Xil_DCacheDisable();

xil_printf("Enabling read Interrupt Handler ...........\n\r"); // Initializing Interrupts
Initial_Interrupt0(XPAR_PS7_SCUGIC_0_DEVICE_ID);

xil_printf("Reading Begins...........\n\r"); // Initial DMA Transfer
Read_Data(0xa000004,256);
c = 'a';
d = Xil_In32(0xa000004);
xil_printf("value = %d\n\r",d);
}
else
{
c='a';
}
return 0;
}
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ISSUES :
1- Reading abrupt values but able to see the correct value.
2- Writing correct values but don't it is uncontrollable.
3- Need a proper explanation.

TroutChaser's picture
TroutChaser
Moderator(18)
Hello,

Hello,
 
It looks like you have a lot going on at once and you did not give us much information. You should always note what version of the Xilinx tools you are using, your host PC OS, what you are trying to accomplish. and a detailed description of the problem. It is not clear to me exactly what problem you are seeing.
 
I doubt anyone will have the time to pore over your whole hardware diagram and your lengthy code snippet, but I do have a couple of suggestions.
 
In your code there is mention of a UART in addition to the ps uart due to needing 9600 baud, but I don't see another UART in your hardware. If you just want to change the baud rate of the ps uart you can take a look at this forum post:
 
http://zedboard.org/content/configure-uart-baud-rate
 
As to the memory interface I would suggest testing your hardware by making direct memory reads and writes before attempting DMA transfers. Then, if that works, start adding DMAs. You might want to look at the example code for the axi dma available in the SDK system.mss.
 
-Gary

prakhar's picture
prakhar
Junior(3)
Hi Gary

Hi Gary

sorry my fault that i din't provided sufficient info.
well my issue is related to read and writes to DDR memory through PL.
i have to store data from PL side into PS DRAM , so i designed this hardware (after watching a plenty of tutorials).
This hardware has some self designed ip cores, with defined functionality :
1- Sample Generator :
#It can generate samples by itself or send user defined signals
#When Enable is '0' it passes user defined signal else samples from counter
#frame size defines size of frame to be transmitted

2-Ip_Read :
#Recives 32 bit data from MM2S port of DMA and displays 8 LSB bits on LED

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Issues :

1- I am able to write to DDR memory from 0 to 64 locations.
2- I am unable to write more than 64 locations.
3- I am unable to read correct data from memory , always there is some abrupt data on output.
4- I am unable to understand the ROLE of MM2S_LENGTH register.

thanks in advance
Prakhar

TroutChaser's picture
TroutChaser
Moderator(18)
Hello Prakhar,

Hello Prakhar,
 
It sounds like the issue is in your custom IP cores. I would suggest looking over the address range and other settings of your IP core. You may also want to take a look at the Xilinx Community forums that focus on this type of development:
 
https://forums.xilinx.com/
 
-Gary
 
 

prakhar's picture
prakhar
Junior(3)
thanks GARY

Hi GARY

thanks for your kind support it helped a lot , there were some addressing issues , which are resolved now and design is working perfectly fine .
Also i want to know a detailed description of MM2S_LENGTH register in AXI_DMA block , if you have some sources please do share .

thanks in advance

-Prakhar

TroutChaser's picture
TroutChaser
Moderator(18)
Hello Prakhar,

Hello Prakhar,
 
If you double click on the AXI_DMA IP block in your Vivado block design and click the 'Documentation' button in the upper left hand corner of the dialog box you should be able to find descriptions of the registers.
 
-Gary

prakhar's picture
prakhar
Junior(3)
Hi Gary

hi Gary

I have that document and also i have read that but there wasn't any detailed description of that register.
I want to know more about that register.

-Prakhar

TroutChaser's picture
TroutChaser
Moderator(18)
Hi Prakhar,

Hi Prakhar,
 
I do not have any more information on the IP block. You might want to try posting a question on one of the Xilinx Community forums, perhaps the one targeting System Logic:
 
https://forums.xilinx.com/
 
-Gary

vinay1204's picture
vinay1204
Junior(0)
axi dma interface on zedboard

Hi prakhar,
I am vinay from india. I am working on same project with followed mr.mohhemad sadri tutorial on youtube.I am getting same problem like In my system interrupt is happening only one time .After that it doing nothing , please tell  me which address you have changed in your code.It will very kind of you to help me.last one week i am working on same thing but unable to find out problem.