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Driving Display Port?

Solved
30 posts / 0 new
steven.bell
Junior(1)
Driving Display Port?

I've got a shiny new UltraZed with the IO base board, and after admiring it sitting on my desk a few days, I'm ready to make it do something. :-)
I'm hoping to drive a display via the Display Port on the base board, but I haven't found any documentation about how to do this.  Is it supported out of the box?  What about the framebuffer, Linux driver support, etc?
Any pointers would be much appreciated.
Thanks!

jbd1986
Junior(19)
I've been trying to get this

I've been trying to get this working as well, with no luck.  We tried routing the IDT clock synthesizer similar to the si570 on the zcu102 reference design, but still no luck.  Can anyone provide a working reference design for the display port?

JFoster
Moderator(67)
Hello Steven and jbd1986,

Hello Steven and jbd1986,

We are currently working on a reference design for the display port. I will respond back when we have it posted.

Thanks,

Josh

jbd1986
Junior(19)
JFoster,

JFoster,
I'm not sure if you absolutely need to include a clock generator (pixel clock) for the xilinx_drm module.  If so, I believe you need to connect one of the outputs of the IDT clock synth on your board similar to the si570 user management clock on the zcu102.
There is an upstream IDT versaclock5 clock driver here: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/...
This driver does not support the 4-output variant which your board has, but modifying it for 4 outputs might not be too difficult.  Also, the upstream driver is slightly different from the latest xilinx kernel driver.  You'll need to use "devm_clk_register" instead of "devm_clk_hw_register" and "of_clk_add_provider" instead of "of_clk_add_hw_provider".
 
Again, I'm not sure if the pixel clock is absolutely necessary, but if so, I wanted to help guide this effort a bit quicker.  I hope that helps.
 
 

jbd1986
Junior(19)
In theory, you could cheat a

In theory, you could cheat a bit by manually configuring the IDT clock synth, and then in xilinx_drm_crtc.c you could comment out the portion where it attempts to set the pixel clock:
 

/* set pixel clock */

ret = clk_set_rate(crtc->pixel_clock, adjusted_mode->clock * 1000);

if (ret) {

DRM_ERROR("failed to set a pixel clock\n");

return ret;

}

 

You would need to make sure that you manually configure the IDT synth clock to whatever rate this was trying to acheive.

jbd1986
Junior(19)
The pixel clock is definitely

The pixel clock is definitely necessary, as removing the si570 from the zcu102 design prevents the displayport output from functioning properly.

AlbertaBeef
Moderator(5)
work in progress ...

jbd1986,

I see that you have been posting on the ZCU102 Base TRD wiki pages.  Are you familiar with that design ?

If yes, I can share my "work in progress ..." to port the ZCU102 Base TRD to the UltraZed 3EG SOM + IO Carrier Card.

Regards,

Mario.

jbd1986
Junior(19)
Mario (AlbertaBeef),

Mario (AlbertaBeef),
I'd definitely be interested to test your HDF file contents with my own firmware setup if you want.  I believe the main point of concern is the routing of the IDT clock synth (I'm guessing output 4) to the "dp_video_in_clk" pin.  It's differential and needs to be converted to the correct voltage single ended clock.  Also, zcu102 TRD vivado design seems to show this si570 clock divided by 2, which seemed odd.
There is another difference in the zcu102 vs Ultrazed, in that the dp aux pins are MIO (27-30) instead of EMIO.  I'm not sure to what degree this could be causing an issue, if any (though it seemed strange to me that one has DP_OE and one has DP_OE_N).

jbd1986
Junior(19)
Mario (AlbertaBeef),

Mario (AlbertaBeef),
 
Note that you don't really need the "Full fledged" TRD.  What you want is most similar to system dm5:
http://www.wiki.xilinx.com/Zynq+UltraScale+MPSoC+Base+TRD+2016.3+-+Desig...
 
Where I think the only additions are basically the si570 and enabling the display port. 

AlbertaBeef
Moderator(5)
private message

Justin,

Look for a pm from me.

Mario.

jbd1986
Junior(19)
Mario, I sent a few PMs to

Mario, I sent a few PMs to you.  I think this forum's messaging system is experiencing difficulties :D
 

mykhani
Junior(0)
Boot.bin file for ultrazed DisplayPort Support

@AlbertaBeef
I am new to this and haven't been through Vivado design workflow before. Could you please suggest where I can find a working boot.bin file just like the one coming with Xilinx UltraScale MPSoC BaseTRD which enables DisplayPort along with the required devicetree bits. I'd greatly appreciate any help on this. Thanks!

mathieu.ruiz
Junior(0)
Hi,

Hi,
What kind of issues do you have (log kernel)? Which kernel version do you have?
https://forums.xilinx.com/t5/DSP-and-Video/ZCU102-Zynq-MPSoC-DisplayPort-clocking/td-p/713910
https://forums.xilinx.com/t5/DSP-and-Video/MPSoC-DisplayPort-no-picture-on-ZCU102/td-p/711388
It seems there is an issue with Vivado and Pelatinux 2016.02.
I also tried to use this version. Now I use the last Openembedded with the kernel linux-xlnx-4.6 2016.04 then drm drivers loads.
DP_AUX works but there is an issue on the pixel clock: 

[    9.084041] [drm:drm_crtc_helper_set_config] 

[    9.084047] [drm:drm_crtc_helper_set_config] [CRTC:27:crtc-0] [FB:47] #connectors=1 (x y) (0 0)

[    9.084053] [drm:drm_crtc_helper_set_config] crtc has no fb, full mode set

[    9.084057] [drm:drm_crtc_helper_set_config] modes are different, full mode set

[    9.084064] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0

[    9.084071] [drm:drm_mode_debug_printmodeline] Modeline 33:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

[    9.084076] [drm:drm_crtc_helper_set_config] connector dpms not on, full mode switch

[    9.084078] [drm:drm_crtc_helper_set_config] encoder changed, full mode switch

[    9.084082] [drm:drm_crtc_helper_set_config] crtc changed, full mode switch

[    9.084086] [drm:drm_crtc_helper_set_config] [CONNECTOR:29:DP-1] to [CRTC:27:crtc-0]

[    9.084090] [drm:drm_crtc_helper_set_config] attempting to set mode from userspace

[    9.084096] [drm:drm_mode_debug_printmodeline] Modeline 33:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

[    9.084108] [drm:drm_crtc_helper_set_mode] [CRTC:27:crtc-0]

[    9.084113] [drm:xilinx_drm_encoder_dpms] dpms: 3 -> 3

[    9.084117] [drm:xilinx_drm_crtc_dpms] dpms: 3 -> 3

[    9.084135] [drm:xilinx_drm_crtc_mode_set] *ERROR* failed to set a pixel clock

[    9.084146] [drm:drm_crtc_helper_set_config] *ERROR* failed to set mode on [CRTC:27:crtc-0]

[    9.181922] udevd[1018]: starting version 3.2.1

[    9.192884] random: udevd urandom read with 34 bits of entropy available

[    9.227460] udevd[1019]: starting eudev-3.2.1

[    9.320192] Mali: Mali device driver loaded

[    9.641083] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.

[    9.684857] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.

[   10.507445] random: nonblocking pool is initialized

[   15.621485] [drm:xilinx_drm_connector_detect] status: 1

[   15.621501] [drm:drm_sysfs_hotplug_event] generating hotplug event

[   15.621540] [drm:drm_fb_helper_hotplug_event] 

[   15.621551] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:29:DP-1]

[   15.622677] [drm:xilinx_drm_connector_detect] status: 1

[   15.654927] [drm:drm_property_unreference_blob] ffffffc069b05400: blob ID: 30 (1)

[   15.655066] [drm:drm_add_display_info] DP-1: Assigning EDID-1.4 digital sink color depth as 8 bpc.

[   15.655136] [drm:drm_mode_debug_printmodeline] Modeline 50:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15

[   15.655144] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE

[   15.655156] [drm:drm_mode_debug_printmodeline] Modeline 78:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a

[   15.655164] [drm:drm_mode_prune_invalid] Not using 720x480i mode: NO_INTERLACE

[   15.655175] [drm:drm_mode_debug_printmodeline] Modeline 79:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a

[   15.655183] [drm:drm_mode_prune_invalid] Not using 720x576i mode: NO_INTERLACE

[   15.655194] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080i" 0 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15

[   15.655202] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE

[   15.655214] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15

[   15.655222] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE

[   15.655233] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a

[   15.655241] [drm:drm_mode_prune_invalid] Not using 720x480i mode: NO_INTERLACE

[   15.655255] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:29:DP-1] probed modes :

[   15.655267] [drm:drm_mode_debug_printmodeline] Modeline 31:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

[   15.655279] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5

[   15.655290] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5

[   15.655301] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5

[   15.655312] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5

[   15.655324] [drm:drm_mode_debug_printmodeline] Modeline 76:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5

[   15.655335] [drm:drm_mode_debug_printmodeline] Modeline 38:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5

[   15.655347] [drm:drm_mode_debug_printmodeline] Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5

[   15.655358] [drm:drm_mode_debug_printmodeline] Modeline 37:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5

[   15.655369] [drm:drm_mode_debug_printmodeline] Modeline 36:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5

[   15.655380] [drm:drm_mode_debug_printmodeline] Modeline 34:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5

[   15.655392] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5

[   15.655403] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5

[   15.655414] [drm:drm_mode_debug_printmodeline] Modeline 44:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5

[   15.655426] [drm:drm_mode_debug_printmodeline] Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa

[   15.655437] [drm:drm_mode_debug_printmodeline] Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5

[   15.655448] [drm:drm_mode_debug_printmodeline] Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5

[   15.655459] [drm:drm_mode_debug_printmodeline] Modeline 56:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa

[   15.655470] [drm:drm_mode_debug_printmodeline] Modeline 66:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa

[   15.655482] [drm:drm_mode_debug_printmodeline] Modeline 35:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa

[   15.655493] [drm:drm_mode_debug_printmodeline] Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa

[   15.655504] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa

[   15.655515] [drm:drm_mode_debug_printmodeline] Modeline 41:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa

[   15.655526] [drm:drm_mode_debug_printmodeline] Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6

[   15.655538] [drm:drm_setup_crtcs] 

[   15.655548] [drm:drm_enable_connectors] connector 29 enabled? yes

[   15.655557] [drm:drm_target_preferred] looking for cmdline mode on connector 29

[   15.655566] [drm:drm_target_preferred] looking for preferred mode on connector 29 0

[   15.655574] [drm:drm_target_preferred] found mode 1920x1080

[   15.655582] [drm:drm_setup_crtcs] picking CRTCs for 4096x4096 config

[   15.655593] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 27 (0,0)

[   15.655609] [drm:drm_crtc_helper_set_config] 

[   15.655619] [drm:drm_crtc_helper_set_config] [CRTC:27:crtc-0] [FB:47] #connectors=1 (x y) (0 0)

[   15.655628] [drm:drm_crtc_helper_set_config] crtc has no fb, full mode set

[   15.655636] [drm:drm_crtc_helper_set_config] modes are different, full mode set

[   15.655647] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0

[   15.655658] [drm:drm_mode_debug_printmodeline] Modeline 30:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

[   15.655667] [drm:drm_crtc_helper_set_config] connector dpms not on, full mode switch

[   15.655674] [drm:drm_crtc_helper_set_config] encoder changed, full mode switch

[   15.655682] [drm:drm_crtc_helper_set_config] crtc changed, full mode switch

[   15.655690] [drm:drm_crtc_helper_set_config] [CONNECTOR:29:DP-1] to [CRTC:27:crtc-0]

[   15.655699] [drm:drm_crtc_helper_set_config] attempting to set mode from userspace

[   15.655710] [drm:drm_mode_debug_printmodeline] Modeline 30:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

[   15.655722] [drm:drm_crtc_helper_set_mode] [CRTC:27:crtc-0]

[   15.655731] [drm:xilinx_drm_encoder_dpms] dpms: 3 -> 3

[   15.655740] [drm:xilinx_drm_crtc_dpms] dpms: 3 -> 3

[   15.655760] [drm:xilinx_drm_crtc_mode_set] *ERROR* failed to set a pixel clock

[   15.663878] [drm:drm_crtc_helper_set_config] *ERROR* failed to set mode on [CRTC:27:crtc-0]

[   25.681479] [drm:xilinx_drm_connector_detect] status: 1

[   35.701481] [drm:xilinx_drm_connector_detect] status: 1

[   45.721483] [drm:xilinx_drm_connector_detect] status: 1

jbd1986
Junior(19)
mathieu.ruiz,

mathieu.ruiz,
I don't have any kernel errors at all actually.  The kernel log is identical to the zcu102 board running the same firmware (different psu_init_gpl.c/h and device tree files of course).  I highly suspect the lack of a proper pixel clock is my current issue (I've just stubbed out the pixel clock set command, with various attempts to route vc5 output 4 at 262.79MHz for 3840x2160@30Hz).
I'm using all xilinx-v2016.4 versions of code for zcu102 and ultrazed builds.
 
 
 
 
 
 

jbd1986
Junior(19)
I got it working with

I got it working with AlbertaBeef's design and the following device tree entries:
https://pastebin.com/6HhScvhi
I backported the upstream versaclock 5 driver and kluged it up a bit to get output 4 working, but AlbertaBeef has an actual driver for the IDT clock synth on this board.
 
AlbertaBeef', Where does that driver come from?
 
 
 

jbd1986
Junior(19)
Actually Here's a new

Actually Here's a new pastebin (Previous pastebin was non-working device tree changes)
https://pastebin.com/rtWB6DYB
 
I was missing the following argument from &xlnx_dp_sub:

xlnx,vid-clk-pl;

 

 

I'm not sure what that setting does yet, but it is crucial to operation.

 

jbd1986
Junior(19)
Mathieu has asked a bunch of

Mathieu has asked a bunch of questions via PM, so I'm answering them here in case anyone else has a similar question:
 
- Could you confirm me that psu_init_gpl.c/h is only used by the FSBL and u-boot, not by the kernel? The kernel only needs device tree files.
yes, FSBL or UBOOT SPL only
 

- Do you have to add an IP to generate a clock on dp_video_clk_in?
IDT_clock_synth -> BUFDS -> BUFG -> dp_video_clk_in
 
 
- You said you backported the versaclock 5 driver, have you shared the source code?
Here is my kludge for xilinx-v2016.4: https://pastebin.com/2DDS1K4x
 
 
- The IDT clock synth has to be configured  manually or by I2C?
I guess that depends on what you're trying to do, but xilinx_drm device tree node needs a pixel clock, which in this case is using the kludge driver, which in turn is communicating via i2c.

gengle
Junior(0)
Where does the this file clk

Where does the this file clk-versaclock5.c exist in the 2016.4 source code? I have been searching for it in the PetaLinux open components, but maybe I am misunderstanding where it should be? 

afirago
Junior(0)
2016.4 doesn't contain this

2016.4 doesn't contain this driver. It was added to Linux kernel later. See https://github.com/torvalds/linux/commits/master/drivers/clk/clk-versacl...
An example of making it work with 4.4 kernel (from 2016.4 petalinux release) might be found here https://github.com/MentorEmbedded/mpsoc-linux-xlnx/pull/1

gengle
Junior(0)
Thank you for your reply, I

Thank you for your reply, I am new to Linux. This makes much more sense now. So one other thing that I have noticed is that the DTS file posted put the display in ARGB8888 mode which is not supported by the 4.4 kernel. Looking at the 4.6 kernel they do support the ARGB8888 mode, but Avnet does not have a project setup for the newer kernel. Is there a direction that you could point me in for using the newer kernel or upgrading the DRM driver?

jbd1986
Junior(19)
xlnx,vid-clk-pl;

So that Boolean ends up setting the XILINX_DP_SUB_AV_BUF_CLK_SRC register in the dp sub module.
#define XILINX_DP_SUB_AV_BUF_CLK_SRC                                                      0x120
 
Which I believe corresponds to this value in the DP register guide: https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html#dp___av_buf_aud_vid_clk_source.html
 
It makes sense now, though there is no mention of this requirement in the zynqmp TRM.

afirago
Junior(0)
vivado project

Hi guys, thanks for this thread! Could you please share Vivado project with the idt_clock_synth? I'm trying to rework basic UltraZed tutorial project for this, but cannot figure out how to make dp_video_in_clk pin available for the zynq_ultra_ps_e_0 on BD. 

afirago
Junior(0)
Figured out how to make dp

Figured out how to make dp_video_in_clk visible/available on the zynq_ultra_ps_e_0, the following line should be added to the preset.xml of the UltraZed board files
<user_parameter name="CONFIG.PSU__USE__VIDEO" value="1"/>

Share Project?

Is there any way you could share the Vivado project you have. I'm actually going through the same stuff now. Anything would be appreciated. Thanks!

mathieu.ruiz
Junior(0)
It it can help, with Vivado

It it can help, with Vivado 2017.1 and the last kernel linux-xlnx 4.9, it works. And it uses vpll to generate the clock, that means it's not necessary to implement a design in the PL part to generate clocks.

Andy1988
Junior(2)
Could you post the part of

Could you post the part of your device tree which configures the display port driver to synthesize the pixel clock internally?

JFoster
Moderator(67)
Helllo Everyone,

Helllo Everyone,

The display port reference design is now posted

http://zedboard.org/support/design/17596/131

--Josh

vishal.bh30
Junior(0)
Hello JFoster,

Hello JFoster,
I am pretty new to all this and was trying my hands on display port. I have Win 7 with Vivado 2017.3 webpack installed. The Display Port tutorial reference that you shared specifically needs linux OS and petalinux. Wanted to know if we can have tutorial made on win OS without petalinux and linux machine ? I do not have a need to create a bootable binary image of my project to be loaded with SD card.

JFoster
Moderator(67)
Hello Vishal,

Hello Vishal,

At this time we do not plan to make a windows version of the design.

--Josh

vishal.bh30
Junior(0)
Hello Josh ,

Hello Josh ,
Ok.
First of all thatnks for the shared tutorial. The image worked fine on my machine (Ultrazed EG).
Is it possible for you to share the step by step tutorial for the linux as well ? specially on the block design ? I also need to modify the content getting displayed instead of a tricube some image... or so..so what steps in sdk or program we can use to do that ?