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Editing wrapper file in VHDL

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przedmarancz's picture
przedmarancz
Junior(0)
Editing wrapper file in VHDL

Hello,
I was going through the tutorial Zynq design from scratch, Part 17( http://svenand.blogdrive.com/archive/176.html#.VHXoDoXtMy1 ), and I got stuck while editing wrapper file and adding my custom logic, could anyone explain how to modify this file in VHDL design, please? Im trying to attach a PWM with clk and dutycycle inputs and pwm_out output: