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FAQ: Warnings in my project

I had a few questions about Warnings so I thought I would post a hopefully concise answer here.

Often it is the case that you will be designing hardware in either VHDL, Verilog, or Schematic Capture and when synthesizing that design you will receive a series of warnings.

First, it is always important to read through all messages that the tools provide, as it will both give you a better understanding of the tools as well as what they are doing.  This will lead to a better functional understanding of how your design is behaving both in simulation and in live silicon.

Second, just because there is a warning within your design does not mean that it will not operate they way that you intended it to do so.  Since VHDL and Verilog are Inferred Languages (this type of language means that you are making suggestions to the 'compiler' rather than telling it exactly what to do), sometimes your inference may not be exactly what the tools are looking for, but still valid within the definition of the language you are using.

Here is a quick example:  A 8x8 bit multiplier.

If we look at the rules of binary multiplication, we see that the result of any multiplication will result in a number that is the size of summation of all of the parts of the multiplication.  So a 8 bit number multiplied by a 8 bit number will result in a 16 bit result.

So the VHDL for this looks like:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity multiplier is
    Port ( clk : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           c : out  STD_LOGIC_VECTOR (7 downto 0));
end multiplier;

architecture Behavioral of multiplier is

-- create a register to place our multiplication
-- product into
signal result : std_logic_vector(15 downto 0);

begin

-- our primary synchronous process
process( clk )
begin
if( rising_edge( clk ) ) then
-- calculate the multiplication product
result
end if;
end process;

-- assign bottom 8 bits of product to output port
c

end Behavioral;

If we synthesize this code, we see in the report that a multiplier and 15 flip-flops are inferred:

Synthesizing Unit .
    Related source file is "C:\Xilinx\projects\warnings_example\multiplier.vhd".
    Found 16-bit register for signal .
    Found 8x8-bit multiplier for signal created at line 41.
    Summary:
inferred   1 Multiplier(s).
inferred  16 D-type flip-flop(s).
Unit synthesized.

We also see within the output of our Synthesis tool, the following 8 warnings:

WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .

These four warnings are created by this line of code:

c

This assigns the bottom 8 bits of our multiplication product to our output port.  Since our multiplication operation actually created 16 total bits of product, the top 8 bits are left unused after this assignment.  This results in a warning since there are hanging bits that are unused - the tool wants to make sure you as the designer know about them incase you wanted to use them.  In this case, we know that we can't use these, thus we will ignore this warning.

UCF/Constraints Warnings:

There are also cases where warnings can occur when creating Zynq processor systems within PlanAhead and/or XPS.  This can occur if pins are not used explicitly when using the XML PS configuration provided for the ZedBoard or the ZC702, but you don't use all of the peripherals within the configuration.  If you actually aren't using the peripherals, you can ignore these warnings as they don't matter to you.

Note: if you are designing your own board, you will want to pay attention to these warnings as you need to make sure the default state for these unused pins don't conflict with interrupts that may be generated within the Zynq PS, or how the pins may effect other aspects of your hardware design.  Reference the DataSheet for Zynq when dealing with this concern.

Hope that helps!  One of the things that exist with all hardware tools that involved coding, you will learn what errors and warnings mean the more projects you work on - so get out there and start hacking!