Sorry, you need to enable JavaScript to visit this website.

HDMI display control driver

Unsolved
3 posts / 0 new
duckcud's picture
duckcud
Junior(0)
HDMI display control driver

Hello experts,
 
I have implemented the HDMI display control design in Vivado 16.2. The design works fine, but there is a small abnormal situation that every time I get DMA error: Start read transfer failed 9, when re-launching the application without newly programing the FPGA. I debug the VDMA register and get following printout:
 
AXI_VDMA - Partial Register Dump (uBaseAddr = 0x43000000):
     PARKPTR          = 0x00000000
     ----------------
     S2MM_DMACR       = 0x00000000
     S2MM_DMASR       = 0x00000000
     S2MM_STRD_FRMDLY = 0x00000000
     S2MM_START_ADDR0 = 0x00000000
     S2MM_START_ADDR1 = 0x00000000
     S2MM_START_ADDR2 = 0x00000000
     S2MM_HSIZE       = 0x00000000
     S2MM_VSIZE       = 0x00000000
     ----------------
     MM2S_DMACR       = 0x00010003
     MM2S_DMASR       = 0x00010003
     MM2S_STRD_FRMDLY = 0x00010003
     MM2S_START_ADDR0 = 0x00010003
     MM2S_START_ADDR1 = 0x00010003
     MM2S_START_ADDR2 = 0x00010003
     MM2S_HSIZE       = 0x00010003
     MM2S_VSIZE       = 0x00010003
     ----------------
     S2MM_HSIZE_STATUS= 0x00000000
     S2MM_VSIZE_STATUS= 0x00000000
     ----------------
AXI_VDMA - Checking Error Flags
 
Is it correct? In the xstatus.h file, it says that the device need to be reset, but I thought that by vfb_common_init and vfb_tx_init the device has already been reset.
 
Do you have any idea about it, how I could solve the error?
 
Best regards, YM

aynilian's picture
aynilian
Junior(0)
HDMI display control driver

Hi YM,
Is it this design:
ZedBoard HDMI VIPP, Vivado 2014.1, if so, how did you get it to work on vivado 2016.2?. I did something similar on vivado 2016.3, but I had to manually create a block design based on the block diagram from a vivado 2014.1 version. I had to get a license for one of the peripherals. In any case, I had to mess around with the clocks. I had to make sure that the VDMA memory to stream access clock was much higher than the 148.5 Mhz HDMI clock. I was getting fifo under-runs in the video stream to video output block.
Even though I was able to see the software program the HDMI ADV7511, and could see the h anf v sync pulses with the clock and dat going out to the HDMI controller chip (ADV7511), I did not see any display on the HDMI connected monitor. The fact that you were able to see something on your monitor display is a good sign. How did you convert the 2014.1 design to 2016.2?

duckcud's picture
duckcud
Junior(0)
Hello,

Hello,
yes, it is. 
>>  I did something similar on vivado 2016.3, but I had to manually create a block design based on the block diagram from a vivado 2014.1 version.
 
Did it mean that you manually created the whole design by manually adding all IP modules? If so, it would be the problem. What I did was to modify the TCL script by manually editing the IP version appropriate to the 2016.2 version. I have done nothing with the clocking and buffer size.
 
Hopefully it would help.
 
Br, YM