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HIL on Zynq

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shakith's picture
shakith
Junior(0)
HIL on Zynq

Hi all,

I am trying to debug the HIL example on the zedboard. Only at the point of calling the AXI transcation (e.g configure_timer(UP_COUNTER, BASE_ADDR_TIMER_1) - WRITE_REG) from the C code, it does a busy waiting. If I step over the line I get remote failure reply error. Also ISIM reports the following errors.

WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_AWADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_AWVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_AWREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_WDATA was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_WVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_WREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_ARADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_ARVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_ARREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_WDATA was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_WVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_WREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_RVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_RREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_RDATA was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_AWADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_AWVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_ARADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_AWREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_ARVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_ARREADY was not found in the design.

Though the bitstream(no programming errors as well) and the simulation models compiled properly, it seems the interface that maps the AXI bus from the real hardware to ISM through JTAG tunneling has a bug.How can i debug this?

I also added the following info the hwcosim.bsp file.

'zed-jtag' => {
'Description' => 'ZC702 (JTAG)',
'Vendor' => 'Xilinx',
'Type' => 'jtag',
'Part' => 'xc7z020-1clg484',
'Clock' => [
{
'Period' => 10,
'Pin' => 'Y9',
},
],
'BoundaryScanPosition' => 1,
},

shakith's picture
shakith
Junior(0)
Hi,

Hi,

I am trying to get HIL example working on the zynq zedboard. At the point of axi transaction, processor waits forever and ISIM also doesn't show any activity on the AXI channels.

These are the steps I followed.
1. Added the following code the hwcosim.bsp
'zed-jtag' => {
'Description' => 'ZC702 (JTAG)',
'Vendor' => 'Xilinx',
'Type' => 'jtag',
'Part' => 'xc7z020-1clg484',
'Clock' => [
{
'Period' => 10,
'Pin' => 'Y9',
},
],
'BoundaryScanPosition' => 1,
},
1. Created a new plan ahead project and a sub xps project targeting the zynq zedboard with a timer peripheral.
2. In xps, removed Fclk0 connection and made clk and reset pin of the axi bus external.
Added the following lines the MHS(attached) for the timer
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
and AXI interconnect
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PARAMETER C_RANGE_CHECK = 0
3. Back in plan-ahead, created the top module and added the test bench too generate the clk and reset.
4. Under behavioral simulation fuse options, added the following
hwcosim_instance /testbench/dut/module_1_i/processing_system7_0 -hwcosim_clock M_AXI_GP0_ACLK -hwcosim_board zed-jtag -hil_zynq_ps
5. Powered the board. Ran behavioral simulation. It managed to successfully download the bit stream.
6. Export and launch SDK and ran in debug mode.
7. Enabled simulation run all
8. In SDK, ran both resume and step mode.
9 . Terminal programs shows "Configuring the timer as an up-counter" and get hung.

Is there a step missing here?
Log file shows bit stream is successfully download to the FPGA.
Diff (attached) of my spec with the reference spec file for given HIL example on ZC702 shows only relevant logical changes.
My setup is Xilinx 14.4 on ubuntu.

How does the axi channles get tunneled through JTAG from the ARM to the ISIM application? Is there a way to verify it in XMD?