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i2c via EMIO on PicoZed board

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brucejones's picture
brucejones
Junior(0)
i2c via EMIO on PicoZed board

I have a PicoZed FMC Gen 2 and a PicoZed 7030 SOM.
My experience with FPGA design consists of going through the tutorials available on this website to define a basic system and generate a minimal FPGA image, so not very much.  I'm using Vivado 2016.3 and can successfully create the bitstream and export to SDK, creating the FSBL which i have incorporated into QNX and can successfully boot that on the board.  Now I want to read the MAC address from the EEPROM on the carrier card via i2c.  I haven't found specific instructions on how to do this so my info just comes from various bits and pieces I have found.
In the ZYNQ processing core I enabled I2C_0 under Peripheral I/O Pins.  This selects EMIO pins by default.  I then right click on the IIC_0 and make it an external port.  I then run synthesis and implementation and when that is done I look at I/O planning in the implementation.  My understanding is that pin assignment is made here which generates constraints that are used when creating the FPGA bitstream.   From the schematics it appears that the I2C signals going to the EEPROM are labeled HDMIO_SCL and HDMIO_SDA and that they are connected to ZYNQ pins H6 and H5 respectively.  In the I/O Ports tab I have configured those pins and set them as Fixed, Bank 35, I/O Std to LVCMOS18, Vcco to 1.8, Drive Strength to 12, Slew Type to SLOW, Pull Type to PULLUP and Off-chip Termination to FP_VTT_50.  Most of those are the default values.  
I have a logic analyzer hooked to the test header at J14.  I see I2C activity when the board powers on.  I think I am seeing the Clock IC getting its config from its EEPROM.  After that when I initiate my I2C access to the MAC EEPROM I see no activity.
Could be sw or hw issues, but I want to rule out hw because I'm much less sure of that side of things.  Are there steps that I have missed or gotten wrong in configuring the I2C to use the EMIO pins?  Anything I should check?
Thanks,
Bruce

JFoster's picture
JFoster
Moderator(48)
Hi Bruce,

Hi Bruce,

I have a few design suggestions for you.

1. I would suggest you to double check your constraints were created correctly.

      a. You can see the constraints that will be used to generate your bitstream by Typing "write_xdc -exclude_physical test.xdc" in the TCL console. Use this as your starting point

     b. Here is an excellent documents to start learning about constraints

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug9...

2. I would suggest you remove your "Pull up Type : PULLUP and Off-chip Termination to FP_VTT_50" 

     a. Please see document UM10204 section 3.1.1 for more information about the SDA and SCL signals

http://www.nxp.com/documents/user_manual/UM10204.pdf

3. Change the drive strength to a higher value. This shouldn't affect your design negatively.

--Josh

Hy Bruce,

Hy Bruce,
Did you solve? I'm facing the same issue: i do not see any activity on iic bus when I try to write/read to/from the eeprom.