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IDT Programming Using Avnet Reference Design

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nima_taie's picture
nima_taie
Junior(0)
IDT Programming Using Avnet Reference Design

I am following Avnet reference design from Github to change the frequency of the U13 which is IDT 8T49N242. Everything goes OK, and I get the message IIC EEPROM Test: PASSED message at the end, however, after I power cycle, I still don’t have new clock frequency from the IDT device.
The reference design is programming the EEPROM which is U14, and it is at address 0xA0. However, the  slave address which is indicated in the pzcc_iic_eeprom_test.c source file is at 0x50. I tried to change it to 0xA0, but then the EEROM test fails. After programming the EEPROM, is there anything else I need to do? Why am I not getting the frequency which I want?
I am using Vivado 2015.4 as the reference design requires.

zedman2000's picture
zedman2000
Moderator(2)
Hi there,

Hi there,

Which PicoZed are you using? The PicoZed 7015 or the PicoZed 7030?

If the program is stating a success, then the IDT EEPROM has been re-programmed. Power-Cycling will force the IDT part to re-initialize using that new configuration. If you are not seeing a difference, you might be programming the same thing over and over. That is one reason I like to use JTAG instead of the SDCARD. Once you program, reboot, that is it. You need to perform extra actions to reconfigure. There are cases where the SDCARD is useful as one binary can be quickly put into MULTIPLE boards and powered on / off to reconfigure the boards.

I'm thinking that we need to look at how you are measuring the clock.

How are you measuring the IDT clock? Are you using an Oscilliscope?
The IDT clock feeds into the PL on one clock capable pin, as well as the MGT1. There are also locations to test the clock output from the IDT part.
Keep in mind that this clock synthesizer has 4 channels of output. You might be on the wrong output.
Which output are you trying to measure? How are you using this in your design? The MGT1 input? The PL clock input? Have you validated your constraints are calling out the correct pins to invoke that clock to feed into your clock tree?

You will see TP31 located on the back of the board (under the PicoZed SOM). This is connected to the same output as the PL clock (although will be out of phase). The other test points are TP34/TP33, TP35/TP36. These test points surround the same area where you will locate the 8T49N242 (U13).

These can be seen defined on page 3 of the schematic. You can find the schematic on the PicoZed documentation page:
http://picozed.org/support/documentation/13076

The 0xA0 and 0x50 are different representations of the address. 0xA0 is 10100000b, where 0x50 is 01010000b, notice the 0x50 is shifted? It has to do with how the values must be presented to the I2C engine. 0x50 is actually the correct value that you need to use in the code.

Included in the design documentation are SDCARD images, which should allow you to reset the clock to the default configuration as well as enable the various MUX capabilities of the part.

Lastly, the file you want to be modifying for this - using the output from the IDT Timing Commander is iic_eeprom_demo.c which is located:
\hdl\Projects\pz_fmc2_valtest\software\pz_fmc2_valtest.sdk\pzcc_iic_eeprom_test\src\
for a PicoZed 7015 and located:
\hdl\Projects\pz_fmc2_valtest\PZ7030_FMC2\pz_fmc2_valtest.sdk\pzcc_iic_eeprom_test\src\
for a PicoZed7030.

This location is mentioned on page 13 of the downloaded reference design documentation.

Contained in that file will be all three example values that were included as SD Card binaries. You will need to provide the values you want into the int8u array default_idt_config, ensure you maintain the same format!!

If you need to validate the SOURCE of that file (pre-building the project, straight from GITHUB), you can locate that:
\hdl\Projects\pz_fmc2_valtest\software\pzcc_iic_eeprom_test\src\iic_eeprom_demo.c

--Dan

nima_taie's picture
nima_taie
Junior(0)
Thanks for the reply

Hello,
Thanks for the reply.
I am using Picozed 7030 SOM. I am also using JTAG to boot 7030. It is faster, and I am only working on one board. I am also using an 2GHz Oscilloscope with both single ended 500MHz probe and differential probe. I am measuring the outputs on the test points you mentioned in your reply. I know that TP31 is inverted version of Q3 output, as the documentation indicates. 
I am programming the IDT device to get HCSL output clocks on channels Q0-Q2 and single ended on Q3. I have modified iic_eeprom_demo.c file to have my config setting in int8 default_idt_config[133] array. I have commented out all ofher configs. I then used IDT's timing commander to create my EEPROM setting as they describe in their EEPROM created app note.
Thanks for clarification on the address. That makes sense. 
What I see is that, what ever I program to IDT device does not appear at the test points. It appears to be programmed to some value which is not even what the default values are. I just got a Total Phase Ardvard, and I am going to attempt to program the IDT or maybe even I2C directly from the PC. I am going to give that a try.
Thanks,
Nima
 

zedman2000's picture
zedman2000
Moderator(2)
Nima,

Nima,
Please let me know how your experiment works. It sounds like you are covering a lot of the troubleshooting tips I would have provided!

Can you tell me what your source clock is?
Are you using the 38.88MHz crystal input?
Are you using the FMC or PCIe path for feeding a clock in?
Do you have access to a way to put a clock on one of those paths?
If so, you would be able to also test the two included BIN files that configures the part as a MUX, which would show that the part is behaving as expected.

Are all Q0-Q2 clocks setup for the same value, or are you using different values for each? I have used some of the lines connected to the Test Points to produce varying clocks, just to validate that I am seeing other programming configurations.

Since you indicated you are using HCSL, are you feeding these clocks off board somehow?
HCSL requires 50ohm to ground. Please see: IDT's AN808 It coveres most of the situations that you would need to account for. https://www.idt.com/document/apn/808-pci-expresshcsl-termination

The PicoZed 7030 has 100Ohm termination at the Zynq part for the MGT inputs (see sheet 4, R91, in the "PicoZed 7015/7030 Schematics Rev C.04" located http://picozed.org/support/documentation/4736) and is AC coupled. That could pose a problem as we have not run the clock with HCSL. We have used LVPECL and LVDS. If you need HCSL, you might need to change the circuitry depending on what you are attaching to the FMCv2. If you are staying onboard, I would suggest you use LVPECL or LVDS.

--Dan

nima_taie's picture
nima_taie
Junior(0)
Application Background

Hi Dan,
Let me give you more background on what I am trying to do with the Picozed, and V2 Carrier Board. 
I am using Picozed board as a PCIe root complex - however, the carrier board is designed to be an end-point PCIe for Picozed. The PCIe REFCLK on PCIe edge are inputs to the IDT and FPGA high speed transceivers. I need to provide a reference clock to both FPGA pins, and also PCIe Edge connector. 
I was hoping to use the output from IDT device to provide a clock to both FPGA and PCIe. I wanted to route TP33/34 or TP35/36 to the pads of R106 after removing R106. The reason for removing it was that PCIe end point devices has the 50Ohm termination. 
I see your point in using different clock values at output of Q0-Q2. However, I don't see any activity. Not even a glitch. I have also changed the output type from HCSL to LVDS, but still no activity. 
I noticed on IDT's data sheet for the clock device, Q0 and Q1 are using CLK0 and CLK1 as reference inputs. I don't have CLK0 and CLK1, but I have changed their input source using Timing Commander to be Q3 rather than Q0 in the PLL section. 
Anyway, I am planning to go off-board to a PCIe end-point device hence the need to for HCSL output. 
What is your recommendation for PCIe REF Clk then? I need to pair of clocks for FPGA MGTs, and one pair for PCIe reference clock on edge? 
Thanks,
Nima

zedman2000's picture
zedman2000
Moderator(2)
Hi Nima,

Hi Nima,

It sounds like you should really be using one of our other products. I would recommend the Mini-ITX. It has reference designs and was designed to be a root complex.

If you are still interested in using the IDT clock, we can certainly take a look at that.
I would also suggest trying to load up the STOCK 250MHz EEPROM image one more time. Validate that the hardware is looking good. From what you are describing, I am afraid that the IDT clock synthesizer might have it's outputs damaged.

If you would like to use the IDT 8T49N242, IDT has a reference board that allows you to easily program as well as interface the 8T chip to other circuits. I would suggest using one of those to prototype with. I highly suggest that chip, although the Mini-ITX does not use it - but this could be added into your product design and evaluated separatly.

I have also spoken with your local XFAE. I tried to bring him up to speed on a few things that I think might be going on.

Please let me know what you find out from testing with the STOCK 250MHz sdcard binary. NOTE, you will have to change your boot configuration jumpers in order to have the PicoZed boot from the SDCARD (as you mentioned above you are using JTAG).

--Dan

nima_taie's picture
nima_taie
Junior(0)
Hi Dan,

Hi Dan,
We have done exactly what you suggested. We just haven't received it Mini-ITX yet. Thanks for all the suggestions. 
I actually got the IDT working as well. I took your advice of not using HCSL output since it DOES need the 50Ohm resistors. 
I am going to mark this as solved, if you don't mind.
 
Thanks,
NIma

zedman2000's picture
zedman2000
Moderator(2)
Nima,

Nima,

I'm glad you closed the loop on this! I am glad we were able to help!

Good luck with your design!

--Dan