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I/O voltage on HS header (J3)?

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jschiefer
Junior(0)
I/O voltage on HS header (J3)?

I am trying to understand whether the ultra96's 60-pin HS connector (J3) supports I/O operation at 1.8 V, as I believe it ought to. The Ultra96 HW User Guide implies that it does, on the bottom of page 7.
But when I look at this in the schematic, I get a little confused. Most of the signals on J3 (I particularly care about the differential ones) are hooked up to bank 65 of U1, whose VCCO is hooked up to VCCO_HP. VCCO_HP is provided by LDOA3 of U33, which is a TI TPS650864 PMIC. If I read the data sheet right, LDOA3 can be programmed to be between 0.7 and 1.5 V. This would imply that the maximum VCCO for Bank 65 would be 1.5 V, not 1.8 V as suggested by the user manual.
What am I missing here?
Thank you very much, and I can't wait to have a board in hand!

JFoster
Moderator(64)
Hello,

Hello,

On page 27 of the schematic is defines VCCO_HP as 1.2V.

On page 7 it defines it as 1.2-3.3V. This is refering to what it can be powered at as per the Zynq UltraScale+ MPSoC ZU3EG device . In this boards application case it was chosen to be at 1.2V.

--Josh

jschiefer
Junior(0)
I see, so it is not meant to

I see, so it is not meant to be configurable, and Bank 65 (and hence, most of the I/O on the 60-pin HS connector J3) is 1.2 V logic only. Makes sense.
Thank you for the quick response!
Jan