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Issue with PCIe Root Complex reference design

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olivierprogin
Junior(0)
Issue with PCIe Root Complex reference design

Hi everyone,
 
I recently tried to use the PCIe Root Complex reference design 2015.2 (available here: http://zedboard.org/support/design/2056/17 )for my master thesis project and faced some weird issues when trying to add a DMA to the reference design.
 
While booting, my linux system was receiving 100'000 interruption from the DMA causing the system to disable the interrupt line and causin the PCIe connection to stop working. A more detailed description is available here: https://forums.xilinx.com/t5/PCI-Express/Adding-a-DMA-to-a-PCIe-design/td-p/818174
 
Now that I had the time to investigate and solve this issue I would like to share the solution with you. To solve this issue, I had to restart a complete design only using the board description files and the constraint file (available here: http://zedboard.org/support/documentation/2056)
 
I then re routed the PCIe bloc with a clock and reset distribuation that made much more sense to me and this solved the issue.
 
You can find block design images on this forum topic here: https://forums.xilinx.com/t5/PCI-Express/Adding-a-DMA-to-a-PCIe-design/td-p/818174
 
I hope this could help anyone in the future
 
Best regards,
Olivier