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LPDDR2 with Zynq 7000

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hb_zed's picture
hb_zed
Junior(0)
LPDDR2 with Zynq 7000

Hi ZedBoard Forum,

i want to create a new design with the Zynq 7000 series(7020). On the new PCB should be a LPDDR2 Memory.

As a reference Design i am using the ZedBoard.

The DDR Memory Controller has the following Limitations,see (TRM UG585,p.294):

Maximum Total Memory Density 1 GB
Total Data Width (bits) 16, 32
Component Data Width (bits) 8, 16, 32
Maximum Ranks 1
Maximum Row Address (bits) 15
Maximum Bank Address (bits) 3

So my question is, can i use the following LPDDR2 with a memory Single Channel S4 Configuration (256 Meg x 32)?

http://www.micron.com/parts/dram/mobile-ddr2-sdram/mt42l256m32d2lk-18-wt

I think the Ranks per channel can be a problem, am i right ?

Thanks for your help!

hb_zed

fletch's picture
fletch
Moderator(15)
If you want to make your life

If you want to make your life easier, I suggest you use one of the parts built into the ZYNQ7 PS configuration menu. I see these two in 2015.1:
 
MT42L64M32D1KL-25
MT42L128M16D1KL-25
 
The part you reference will be a problem for the Zynq PS built-in DDR controller due to the rank. Zynq only has 1 CS, and the part you show requires 2.
 
I also suggest you search the Xilinx forums. A search for "Zynq LPDDR2" returns 50 discussions.
http://forums.xilinx.com/t5/forums/searchpage/tab/message?filter=labels&...
 
Bryan

hb_zed's picture
hb_zed
Junior(0)
128 Meg x 64

Thanks Bryan for your fast answer.

So that means i could use the 128 Meg x 32 configuration right ?

I also thinking about to connect the 2 CS wire in the Layout, do you think it is possible ?

fletch's picture
fletch
Moderator(15)
You could use the 128M x 32,

You could use the 128M x 32, or you could use two of the 256M x 16, but that complicates your layout.
 
Connecting the two CS wires in layout will not allow the controller/memory to work properly.
 
Bryan

leyiran's picture
leyiran
Junior(0)
I have a  LPDDR 2  (KEP04GSC

I have a  LPDDR 2  (KEP04GSC-MABDMKAM1C32),the fsbl of zedboard give the message below:
PCW Silicon Version : 3.0
Xilinx First Stage Boot Loader
Release 2014.3  Dec 19 2016-11:16:20
DDR_INIT_FAIL
FSBL Status = 0xA007
In FsblHookFallback function
how can I solve the problem?
 

JFoster's picture
JFoster
Moderator(48)
Hello Leyiran,

Hello Leyiran,

Try looking at the links Bryan pointed to above first.

https://forums.xilinx.com/t5/forums/searchpage/tab/message?filter=labels...

--Josh