Sorry, you need to enable JavaScript to visit this website.

Memory Interface Generator(MIG) in Vivado

Unsolved
7 posts / 0 new
lukwolf
Junior(0)
Memory Interface Generator(MIG) in Vivado

Anyone know how to set the MIG for Zedboard Development Kit?

TroutChaser
Moderator(18)
MIG is used to generate a

MIG is used to generate a memory controller in the FPGA programmable logic (PL). The only DDR memory on the ZedBoard is connected to the Processor Section (PS) and is not directly connected to the PL section of the Zynq device so you cannot use MIG in this instance.
 
-Gary

lukwolf
Junior(0)
MicroBlaze

Gary, do you have some project with Zedboard plate where've implemented the MicroBlaze? Could you send it to me? My problem is that all the examples I have found do not work.Thank you

Regards, Luca

TroutChaser
Moderator(18)
We do not have any current

We do not have any current examples of MicroBlaze on ZedBoard. You might take a look at Xilinx XAPP1093 as a place to start.:
 
http://www.xilinx.com/support/documentation/application_notes/xapp1093-a...
 
-Gary

lukwolf
Junior(0)
Problem

I try this example and dont work, even i've debugged the project with the boot.bin generated by the author and does not work.

Maxxx54
Junior(0)
Thank you for reply. So the

Thank you for reply. So the only way to interface DDR is thought PS?
Is this correct for all Zynq devices? or only for Zedboard?
What would actually happen if I create only a 'PL' project with MIG IP on Zedboard, since it's providing this option? Moreover it provides an option to have both PS with DDR3 access and a MIG generation as well. Am I missing something?
Thank you in advance.

JFoster
Moderator(69)
Hello Maxxx54,