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minized - [Place 30-58] IO placement is infeasible

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acapon's picture
acapon
Junior(0)
minized - [Place 30-58] IO placement is infeasible

Hi Guys,
 
I have the 2017.2 Vivado project from github, I have built this and generated a petalinux buils which boots on the minized.
 
My next task was to add some IP, as an initial simple test I have just changed the axi_gpio_1 to dual mode and added an output mapped to M9, I have the following set in the constraints file:
set_property PACKAGE_PIN M9 [get_ports pl_gpio_test]

set_property IOSTANDARD LVCMOS33 [get_ports pl_gpio_test]

 

 

 

When I generate in vivado I get the following error:

 
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).

The following Groups of I/O terminals have not sufficient capacity:

 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  Out  RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 1 sites.

        Term: pl_gpio_test_tri_o[0]

 

 

If I look at the I/O bank properties in vivado  the output is correct on bank 35, pin M9, LVCMOS33, output.

 

I'm a bit stumped by this, I have been using a zybo board before and have not seen this error before and there doesn't seem to be much about it on the internet.

 

Anyone got any ideas?

 

Cheers

 

Andy

 

 

 

 

acapon's picture
acapon
Junior(0)
Ok, fixed it. I changed the

Ok, fixed it. I changed the constraints to:
 
set_property PACKAGE_PIN M9 [get_ports pl_gpio_test_tri_o]
set_property IOSTANDARD LVCMOS33 [get_ports pl_gpio_test_tri_o]

 

 

Why am I having to add a _tri_o to the end of the port name in this project?

 

Cheers

 

Andy

acapon's picture
acapon
Junior(0)
Ok, fixed it. I changed the

Ok, fixed it. I changed the constraints to:
 
set_property PACKAGE_PIN M9 [get_ports pl_gpio_test_tri_o]
set_property IOSTANDARD LVCMOS33 [get_ports pl_gpio_test_tri_o]

 

 

Why am I having to add a _tri_o to the end of the port name in this project?

 

Cheers

 

Andy

zedhed's picture
zedhed
Moderator(25)
RE: minized - [Place 30-58] IO placement is infeasible

Hi Andy,

Vivado appends your signal name with "tri_i" or "tri_io" or "tri_o" depending on the IO type when the Create HDL wrapper script generates the wrapper. The appended name depends on whether the signal is defined as input only, input/output, or output only respectively within your GPIO block.

For information on tracking down IO placement errors, see the discussion on this Xilinx thread:

https://forums.xilinx.com/t5/Implementation/IO-Standard-default-when-XDC...

Best Regards,

-Kevin

acapon's picture
acapon
Junior(0)
Hi Kevin,

Hi Kevin,
 
Thanks very much for the info and the link, I will read it carefully,
 
All the best
Andy