Sorry, you need to enable JavaScript to visit this website.

PicoZed SDR configuration process

Unsolved
1 post / 0 new
banksbh
Junior(0)
PicoZed SDR configuration process

I have seen examples using Mathworks Simulink, communications toolbox, HDL Coder, and embedded coder.
The examples use the Workflow advisor for channel mapping and setting up the rx and tx paths. Also, the system blocks can be separated into what will be part of the ARM section and what will be part of the FPGA fabric section.
My question is on how this can be accomplished using Mathworks Simulink and the Xilinx Vivado design suite and System generator. I have designed a system using the Xilinx blockset which I can generate the binary data stream. I wasn't sure the process for implementing the ARM section and linking it with the FPGA portion. I have seen some c code examples on setting up the hardware, setting Tx and Rx freqs, BWs, etc. I wasn't sure the exact process. Are there any examples that show how this is done? Also, is there info on configuring the ports for the signaling. I figure this is done with the constraints file, but details on how this is implemented would be greatly appreciated.
Thanks in advance,
Brian