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PL to DDR Memory Transfer Questions

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PL to DDR Memory Transfer Questions


I am trying to use the AXI CDMA IP to transfer data from the PL to the DDR memory. I have a Zedboard and I am using the UG873 (V14.2) July 27,2012 user guide as a reference. I am using Version 1.3 and the Zedboard so a couple adjustments in the procedure need to be made to use this user guide. That said, I completed the exercise in Chapter 6 using the standalone application software design. This makes a DMA transfer from one DDR memory location to another. Not sure why you would ever want to that but it does work.

I then added PL to control the LEDs and read the switches and push buttons on the Zedboard. I also added a 32 bit counter to the PL that I will simulate my DMA source with. This counter and the push button switches control the counter value and state. I also added a general input and output port to the processor design that I use to preset some values of the counter and to verify the PL performance. I then modified the standaloane software example to adjust the LEDs and monitor the switches. All these changes were made and passed my testing which include performing the memory to memory example DMA transfer. So far no problem but I have not strayed to far from this and other examples available.

Now to do what I really want to do which is DMA transfer from the PL to the DDR memory. I have not seen and could not find an example of this so I have tried to step out on my own.

1. I changed the DMA source from S_AXI_HP0 slave to an AXI external slave connector. This was recommended in another posting and made sense to me. There are other AXI interface options but I figured a slave port for a slave port would work.

2. I then assigned an address to the AXI external slave connector to an address out of the DDR memory range. Since this port is external to the processor, I assumed it would need some space of its own. Since the Zedboard DDR memory ends at 0x1ffffff I assigned it to 0x20000000.

3. Since I am not sure which inputs are need to signal valid data, I made all the input data ports of the AXI external slave connector external connections. I did try just the ones I thought were related to reading from the PL but that did not work either so I selected all of them and set them using the switches on the Zedboard. The only input not connected to the switches is the M_AXI_RDATA which I connected to my counter value.

4. Using this setup I did a Design Check without any errors and then successful generated the netlist.

5. I connected the external ports of the AXI external slave port to my PL logic n PlanAhead . I then generated a bit file successfully.
6. Now I exported the hardware and bit file and started SDK. I ran the stand alone program and now I get the "XAxiCdma_Interrupt: Failed" message. When I step through the program it gets an error servicing the interrupt. I added print statements before and after the DMA transfer is initiated and there is not change in the memory location where the DMA is supposed to be writing. I have tried adjusting the external inputs with the switches and I get the same error regardless of the input setting

Has anyone successfully made DMA transfers from PL to DDR memory?
What inputs does the DMA slave source need to find the data?
How to configure the DMA controller to look at the AIX external slave connection?
Any suggestions or thoughts would be greatly appreciated.


Error on ug873?

On that tutorial, they say to fix the addresses of HP ports to 0x20000000-0x2FFFFFFF and 0x30000000-0x3FFFFFFF but I keep getting this error in DRC:

ERROR:EDK - processing_system7_0 (processing_system7) - C_S_AXI_HP2_BASEADDR has an allowable range of 0x00000000 to 0x1FFFFFFF.

Am I doing something wrong? Thank you

error on ug873

That example is for the xilinx board that has 1G of memory. The Zedboard only has 513M (0x1ffffff).

Axi external slave connections

Hello Ted,
I AM WORKING ON THE SAME lines, we need to define the address of the external slave as it doesnt know the address of the slave connector as it is out of the processor system.
Have you figured out how to make connections to the axi external slave.
so FAR I didnt test my design on the FPGA but will do it in the next days. SO if u have some solution pleas epost it.

Thanks in advance

with regards

I'm working on the same problem

Hello everybody!

I'm trying to work with AXI CDMA but I'm facing an error that I'm not able to solve. I read chapter 6 in "Zynq-7000 All Programmable SoC: Concepts, Tools and Techniques (CTT)" and instatiated a CDMA in the PS. I used HP1 and HP3 instead of HP0 and HP2. I configured base and high address for HP1 as 0x00000000 and 0x00000FFF, while base and high address for HP3 as 0x00003000 and 0x00003000. Then I wrote a simple C program that initializes source and destination memories, programs DMA and reads destination memory after a transfer has been finished.
Results: destination memory contains original values, like no trasfer has been executed, and the status register contains (bit 14 to 0) 101000000100010, wich means: interrupts are generated (bit 14 and 12), DMASlvErr (bit 5) and idle status (bit 1).

Maybe I miss something?

Thanks in advance,


ug873 chapter 6 - before testing application, kernel hangs

Hello everybody!
I completed the project in Chapter 6 in the UG873 CTT file, so i want to run the corresponding software application on my Zedboard. I create the BOOT.BIN file with fsbl,system.bit,u-boot.elf files using "Xilinx Tools"->"Create Boot Image" in SDK14.2.
At last, i copy BOOT.BIN, zImage, devetree, ramdisk8M.image.gz file to SD and power on Zedboard(SD Mode). But linux kernel do not boot successfully, it stop at "[ 0.540000] xgpiops e000a000.gpio: gpio at 0xe000a000 mapped to 0xe080a000". That means there is no output on terminal below this line.
Any suggestions? Thanks!!!


Kernel output stop at there

U-Boot 2012.04.01-00304-g7639205-dirty (Nov 28 2012 - 10:52:48)

DRAM: 512 MiB
WARNING: Caches not enabled
Using default environment

In: serial
Out: serial
Err: serial
Net: zynq_gem
Hit any key to stop autoboot: 0
Copying Linux from SD to RAM...
Device: SDHCI
Manufacturer ID: 2
OEM: 544d
Name: SE04G
Tran Speed: 25000000
Rd Block Len: 512
SD version 2.0
High Capacity: Yes
Capacity: 3.7 GiB
Bus Width: 4-bit
reading zImage

2519768 bytes read
reading devicetree.dtb

5789 bytes read
reading ramdisk8M.image.gz

5031065 bytes read
## Starting application at 0x00008000 ...
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0
[ 0.000000] Linux version 3.3.0-digilent-12.07-zed-beta (root@ubuntu) (gcc version 4.6.1 (Sourcery CodeBench Lite 2011.09-50) ) #2 SMP PREEMPT Sun Dec 23 17:44:28 CST 2012
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: Xilinx Zynq Platform, model: Xilinx Zynq ZED
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] BUG: mapping for 0xf8f00000 at 0xfe00c000 out of vmalloc space
[ 0.000000] BUG: mapping for 0xe0000000 at 0xfe000000 out of vmalloc space
[ 0.000000] BUG: mapping for 0xffff1000 at 0xfe200000 out of vmalloc space
[ 0.000000] PERCPU: Embedded 7 pages/cpu @c1489000 s5696 r8192 d14784 u32768
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 125824
[ 0.000000] Kernel command line: console=ttyPS0,115200 root=/dev/ram rw initrd=0x800000,8M earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=0
[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 240MB 256MB = 496MB total
[ 0.000000] Memory: 489784k/489784k available, 34504k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xe0800000 - 0xfd000000 ( 456 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0440774 (4322 kB)
[ 0.000000] .init : 0xc0441000 - 0xc0468640 ( 158 kB)
[ 0.000000] .data : 0xc046a000 - 0xc0498580 ( 186 kB)
[ 0.000000] .bss : 0xc04985a4 - 0xc04affb4 ( 95 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Verbose stalled-CPUs detection is disabled.
[ 0.000000] NR_IRQS:128
[ 0.000000] xlnx,ps7-ttc-1.00.a #0 at 0xe0800000, irq=43
[ 0.000000] Console: colour dummy device 80x30
[ 0.000000] Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816)
[ 0.090000] pid_max: default: 32768 minimum: 301
[ 0.090000] Mount-cache hash table entries: 512
[ 0.090000] CPU: Testing write buffer coherency: ok
[ 0.090000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.100000] smp_twd: clock not found: -2
[ 0.100000] Calibrating local timer... 399.37MHz.
[ 0.170000] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.170000] Setting up static identity map for 0x304ca8 - 0x304cdc
[ 0.270000] CPU1: Booted secondary processor
[ 0.310000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.310000] Brought up 2 CPUs
[ 0.310000] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
[ 0.320000] devtmpfs: initialized
[ 0.320000] ------------[ cut here ]------------
[ 0.320000] WARNING: at arch/arm/mm/dma-mapping.c:198 consistent_init+0x70/0x104()
[ 0.330000] Modules linked in:
[ 0.330000] [<c0012920>] (unwind_backtrace+0x0/0xe0) from [<c001e924>] (warn_slowpath_common+0x4c/0x64)
[ 0.340000] [<c001e924>] (warn_slowpath_common+0x4c/0x64) from [<c001e954>] (warn_slowpath_null+0x18/0x1c)
[ 0.350000] [<c001e954>] (warn_slowpath_null+0x18/0x1c) from [<c04455a8>] (consistent_init+0x70/0x104)
[ 0.360000] [<c04455a8>] (consistent_init+0x70/0x104) from [<c000858c>] (do_one_initcall+0x90/0x160)
[ 0.360000] [<c000858c>] (do_one_initcall+0x90/0x160) from [<c044185c>] (kernel_init+0x84/0x128)
[ 0.370000] [<c044185c>] (kernel_init+0x84/0x128) from [<c000dfcc>] (kernel_thread_exit+0x0/0x8)
[ 0.380000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.380000] ------------[ cut here ]------------
[ 0.390000] WARNING: at arch/arm/mm/dma-mapping.c:198 consistent_init+0x70/0x104()
[ 0.390000] Modules linked in:
[ 0.390000] [<c0012920>] (unwind_backtrace+0x0/0xe0) from [<c001e924>] (warn_slowpath_common+0x4c/0x64)
[ 0.400000] [<c001e924>] (warn_slowpath_common+0x4c/0x64) from [<c001e954>] (warn_slowpath_null+0x18/0x1c)
[ 0.410000] [<c001e954>] (warn_slowpath_null+0x18/0x1c) from [<c04455a8>] (consistent_init+0x70/0x104)
[ 0.420000] [<c04455a8>] (consistent_init+0x70/0x104) from [<c000858c>] (do_one_initcall+0x90/0x160)
[ 0.430000] [<c000858c>] (do_one_initcall+0x90/0x160) from [<c044185c>] (kernel_init+0x84/0x128)
[ 0.430000] [<c044185c>] (kernel_init+0x84/0x128) from [<c000dfcc>] (kernel_thread_exit+0x0/0x8)
[ 0.440000] ---[ end trace 1b75b31a2719ed1d ]---
[ 0.440000] NET: Registered protocol family 16
[ 0.460000] L310 cache controller enabled
[ 0.460000] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72060000, Cache size: 524288 B
[ 0.460000] registering platform device 'pl330' id 0
[ 0.470000] registering platform device 'arm-pmu' id 0
[ 0.470000]
[ 0.470000] ###############################################
[ 0.480000] # #
[ 0.480000] # Board ZED Init #
[ 0.480000] # #
[ 0.490000] ###############################################
[ 0.490000]
[ 0.500000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.500000] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.530000] xslcr xslcr.0: at 0xF8000000 mapped to 0xE0808000
[ 0.540000] bio: create slab <bio-0> at 0
[ 0.540000] gpiochip_add: registered GPIOs 0 to 245 on device: xgpiops
[ 0.540000] xgpiops e000a000.gpio: gpio at 0xe000a000 mapped to 0xe080a000

Please, Thanks everybody!!!

Mapping a Slave

Hello Coolwood,

I can not map (klicking on "generate Addresses") any types of slaves into my CDMA design. Do you found a solution to map a Slave into your CDMA Design?

PL to DDR Memory Transfer

Hi Coolwood:
I have started to work on zynq recently.
Were you successful in connecting DMA controller between PL and PS?
If yes, please share the reference material/suggestions.
Thanks in advance

Address of HP AXI Slave

as some of you managed to complete chapter 6 in "Zynq-7000 All Programmable SoC: Concepts, Tools and Techniques (CTT)" I hope somebody can help me.
I expected to find the addresses of HP0 and HP2 in the file xparameters.h or any other file in the directory but I could not, nor did the compiler!
In the file cdma_app.c there are the statements:

static u32 SourceAddr = XPAR_PS7_DDR_0_S_AXI_HP0_BASEADDR;
static u32 DestAddr = XPAR_PS7_DDR_0_S_AXI_HP2_BASEADDR;

I cannot find these base addresses or anything else that would match.
I assigned the addresses in the Vivado Address Editor, generated the Block design, created the board support package, generated the bitstream and exported everything to SDK. So what might there be wrong?


Addresses of HP AXI Slave

The example in the guide was done in EDK so because you are using Vivado you won't have the same xparameters.h file. You should do something like this:

static u32 SourceAddr = XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x10000000;
static u32 DestAddr = XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x20000000;

If you are planning to send the data from the DDR, you do not want to start at BASEADDR because that's were the code is being written from.

My problem is that I connected cdma_introut on the CDMA to IRQ_F2P on the PS, but I can't find the interrupt definitions. If you know where to find them please let me know.