Sorry, you need to enable JavaScript to visit this website.

PlanAHead and VHDL-Verilog design

Unsolved
8 posts / 0 new
guillaume_bres's picture
guillaume_bres
Junior(0)
PlanAHead and VHDL-Verilog design

A simple question

what is the best way to design and debugg some vhd file when you are creating and working on a project from planAhead - xps?

i got used to creating my stuff with these two - they are really great once we have gone through the tutorial. And i start creating more complex projects which involve writing my vhd code.
by now i used to write it by hand, mostly modifying "user_logic.vhd" but now i would like to create different level of implemantations and i need syntax debugging, and to me, it is not obvious how we are supposed to do so.

At now the only solution i came up with was to create an ise project with my vhd files including user_logic, doing my work, and then copy the result back into my planAhead project.

tusu's picture
tusu
Junior(0)
PlanAHead and VHDL-Verilog design

Hi,

Dont be messed up with the software varities..

in ISE you can write your HDL code,synthesize it...You have to only move to planahead while giving the Pin constraints.and .bit can also be generated in ISE itself..

Also the whole work can be done on planahead as well

guillaume_bres's picture
guillaume_bres
Junior(0)
thanks for your answer.

thanks for your answer.

general process using planAhead links us to generate a .bit and different kind of folders, mainly IPCORE where we are supposed to code our own vhdl.

my personnal vhdl is programmed inside ISE.
if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?

samely i dont see how you would link a proper ise project including one or many .vhd constrained by one .ucf to a planAhead project ready to be deployed on the zedboard (since planAhead allows us to create a .ucf for our application .ucf which is located to a particular place, which is /project/constr/new/my.ucf )

tusu's picture
tusu
Junior(0)
Comments on your reply_ bres

Home → Forum → General Questions
PlanAHead and VHDL-Verilog design
published by guillaume_bres on Mon, 2014-02-10 12:26
Forums:
General Questions

A simple question

what is the best way to design and debugg some vhd file when you are creating and working on a project from planAhead - xps?

i got used to creating my stuff with these two - they are really great once we have gone through the tutorial. And i start creating more complex projects which involve writing my vhd code.
by now i used to write it by hand, mostly modifying "user_logic.vhd" but now i would like to create different level of implemantations and i need syntax debugging, and to me, it is not obvious how we are supposed to do so.

At now the only solution i came up with was to create an ise project with my vhd files including user_logic, doing my work, and then copy the result back into my planAhead project.

Send author a message
Subscribe
Report Spam

Share on facebook Share on twitter Share on google
PlanAHead and VHDL-Verilog design
Permalink Submitted by tusu on Sun, 2014-02-16 13:39.

Hi,

Dont be messed up with the software varities..

in ISE you can write your HDL code,synthesize it...You have to only move to planahead while giving the Pin constraints.and .bit can also be generated in ISE itself..

Also the whole work can be done on planahead as well

reply

thanks for your answer.
Permalink Submitted by guillaume_bres on Mon, 2014-02-17 15:55.

thanks for your answer.

general process using planAhead links us to generate a .bit and different kind of folders, mainly IPCORE where we are supposed to code our own vhdl.

"my personnal vhdl is programmed inside ISE.
if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?"

In ISE you will generate the .bit which get implemented on the PL of your zed board and if also get implemented on planahed then again it will also configure the PL portion..It has nothing to do with CPU PS7. CPU PS7 is hard core though it is programmable but not by .bit, in SDK PS7_init.tcl file will program PS7. Make one thing clear that if you upload .bit in ZED then only PL is getting used.

@ your 2nd qsn, in .ucf, you can put your constraints that could be pin number,area constraints , time constraints, if you have many .vhd then you can create a top module, which can all constraints..In ISE or plan-ahead you can do so.

tusu's picture
tusu
Junior(0)
Comments on your reply_ bres

"my personnal vhdl is programmed inside ISE.
if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?"

In ISE you will generate the .bit which get implemented on the PL of your zed board and if also get implemented on planahed then again it will also configure the PL portion..It has nothing to do with CPU PS7. CPU PS7 is hard core though it is programmable but not by .bit, in SDK PS7_init.tcl file will program PS7. Make one thing clear that if you upload .bit in ZED then only PL is getting used.

@ your 2nd qsn, in .ucf, you can put your constraints that could be pin number,area constraints , time constraints, if you have many .vhd then you can create a top module, which can all constraints..In ISE or plan-ahead you can do so.

guillaume_bres's picture
guillaume_bres
Junior(0)
ok thanks a lot things are

ok thanks a lot things are clear now

rtt123's picture
rtt123
Junior(0)
Doubt about the Clock

I am working on ZedBoard.
Can you help me to find PL clock pin(Y9) on the Board.
How to manage this clock frequency(100 Mhz) into different clock frequency to enter as main clock of the design i.e how do I manage the clock.

TroutChaser's picture
TroutChaser
Moderator(18)
Rajesh,

Rajesh,
 
As you can see on the ZedBoard schematic, or as is detailed in the ZedBoard Users Guide (section 2.5), the Zynq GCLK input on Y9 is connected to IC17, which is an oscillator. Both documents can be found here:
http://zedboard.org/support/documentation/1521
 
You can use one of the clock management blocks in the Zynq PL (Programmable Logic) section to manage the clock.
 
In the future you would be better served to start a new forum topic rather than add a post to an older and unrelated thread.
 
-Gary