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PWM in 7 series FPGA to control 4 BLDC

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andrea_r's picture
andrea_r
Junior(0)
PWM in 7 series FPGA to control 4 BLDC

I want to control 4 BLDC motors with 24 PWM wave (6 signals for each motor).How can I generate these waves?
Moreover, I would like to send these signals with small delays between them, how can I do it?

Furthermore, I would like to simultaneously sample the currents flowing in the motor at a particular instant of time (for example when the corresponding PWM signal is high).
Since I have these delayed PWM, could I get any problems during sampling of the currents?

mbrown's picture
mbrown
Moderator(7)
FPGA-based PWMs are easily

FPGA-based PWMs are easily created with a few lines VHDL or Verilog code. A counter sets the resolution and a comparator sets the duty cycle.  Adding delays to adjacent PWMs to reduce EMI spikes at the inverter stage takes just a little more code.
 
Simultaneous sampling, synchronized with a PWM value (or inactivity) is also straightforward.
 
The 6-step controller code for the follow kit is open-source, available on GitHub.  You might find some inspiration there.
https://wiki.analog.com/resources/eval/user-guides/ad-fmcmotcon2-ebz
 
/Matt
 
 
 
 

mbrown's picture
mbrown
Moderator(7)
FPGA-based PWMs are easily

FPGA-based PWMs are easily created with a few lines VHDL or Verilog code. A counter sets the resolution and a comparator sets the duty cycle.  Adding delays to adjacent PWMs to reduce EMI spikes at the inverter stage takes just a little more code.
 
Simultaneous sampling, synchronized with a PWM value (or inactivity) is also straightforward.
 
The 6-step controller code for the follow kit is open-source, available on GitHub.  You might find some inspiration there.
https://wiki.analog.com/resources/eval/user-guides/ad-fmcmotcon2-ebz
 
/Matt
 
 
 
 

andrea_r's picture
andrea_r
Junior(0)
Thanks for the reply.

Thanks for the reply. Moreover, I don't understand a thing about the ADC. Reading the reference manual Zynq-7000 AP (UG585), I see that the chapter "XADC interface" talk about LogiCORE IP AXI XADC core.
Then, this core logic is already present in all 7000 series chip or it be added externally?

In particular, I would like to use the "event-driven sampling mode" of the ADC (see in UG480), but reading the product guide of LogiCORE IP AXI XADC (see PG019).
Then, this core logic is necessary in order to use the event-driven mode?

I would like sampling 12 current signals (3 for each motor).