A great question was posted by maw41 on the forums today: http://zedboard.org/content/onboard-ethernet-fpga
maw41 wanted to know if he could pull the signals for the Ethernet MAC within the Processing System (PS) of the Zynq-7000 AP SoC device, out through the Programmable Logic (PL). The answer is yes!
I thought I would take this opportunity though to talk about how to move signals from the MIO pins (those that are dedicated to the MIO Bank) to the EMIO pins (those that are available to the PL).
First, create a PlanAhead project targeting your Zedboard and add an embedded source (to see how to do this check out this forum post: http://zedboard.org/content/zedboard-create-planahead-project-embedded-processor
Once you have completed the BSP Wizard, you will be presented with the main screen displaying System Assembly View that looks like this:
Find the I/O Peripherals list on the left side of the PS and click on it.
After you click the IO peripherals list you will see that the same list of peripherals displayed in the System Assembly View, is now displayed in a pop-up with additional configuration information.
Now for maw41, they will select the Enet 0 option and switch the selection from "MIO 16 .. 27" to "EMIO". EMIO is an internal bank of IO that dumps directly into the PL of the Zynq device. In the event that you as a designer wanted to configure any additional ports, this is the same process you would follow, however you would select different peripherals.
Now, here it is important to note that not all peripherals are supported within EMIO. An example of this is USB. There are dedicated PHY's within the IO structures of the MIO bank that are needed to use USB. These primitives do not exist within the PL portion of the device. Take some time to play around with what peripherals can and can not be used via EMIO.
Next, we will check to ensure that our Enet 0 device was correctly placed within our Ports tab within the System Assembly View. Click the Ports tab on the top of the System Assembly View and explained the the "processing_system7_0" item within the list. Under that item, the tree will be populated with the various external ports the PS has. Scroll down and you should see a line that reads: "(IO_IF) ETHERNETIF_0 ... Not Connected". Great! We have successfully added the Enet 0 peripheral to the Ports list, now we just need to connect it to the internal EMIO bank within the PS.
To connect the port to the EMIO pins we will need to select the pull down that currently says "Not Connected to External Ports" and select "Make Ports External". This will cause the Stub that gets generated within PlanAhead to include these signals within it, so they can be used within the PL.
That's it! Run your Design Rule Check (DRC) check, and save your project. Once you exit XPS you will be back to PlanAhead and you can create your Stub HDL wrapper for your processing sub system by choosing "Create Top HDL" from the right mouse click menu on your module_1 source file. (if you are having trouble with this, check out the blog post I linked in the beginning of this post). Once you have generated your stub you will be able to browse to see that it includes your added ports:
Well that is the flow for switching between MIO and EMIO pins on the Zynq-7000 APP SoC using PlandAhead and XPS.