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Regarding Cache and DMA

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Regarding Cache and DMA

I have two questions regarding cache:

1. Should I invalidate the cache for the source/ destination memory on DDR for a DMA execution or the cache management unit does it?

2. If I disable the cache, can I use the L2 cache memory(512KB) as an on chip memory(Similar to SRAM)?

Hello Prathima,

Hello Prathima,
This Xilinx Answer Record might help with question 1:
If you still have questions regarding cache and DMA I would suggest posting the question on one of the Xilinx community forums:
The answer to question 2 is discussed in the post on the Xilinx community forums:
If you do want to try to 'lock' a segment of code in the L2 Cache and execute it these links might be useful: