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Syncing microzed with external ADC (clocking)

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smvo555's picture
smvo555
Junior(0)
Syncing microzed with external ADC (clocking)

We would like to use the microzed for a program at our company.

The product we are developing needs to be synced with the DC0 + and - outputs from a 500 MHZ ADC.(the fpga fabric needs to capture the data and receive the clock signal.

After reading the documentation I believe that we can use the clock capable inputs on the microheader to sync the fabric with the 500MHz DCO(+/-) outputs from the ADC.

However, some other posts on this form I've read regarding the capability of using an external oscillator have made me think that maybe this is not so strait forward.

I'd appreciate anyone's input regarding the feasibility of the task I've outlined above before ordering several microzed boards.

Thanks!
Sam

TroutChaser's picture
TroutChaser
Moderator(18)
Depends

That is an interesting question. A lot depends on the ADC you are using. At those speeds at the very least the ADC clock would need to be source synchronous and would need to have an internal digital pattern generator to generate a know sequence to the FPGA for the purpose of calibration. Per one of my colleagues:
 
At 500 MHz, a calibration circuit is absolutely necessary to align the clock and data for proper set-up time at the input to 1st synchronous element in the FPGA for error-free capture of the ADC data. This calibration sequence is usually issued at power-up, during which time the ADC is placed in pattern generation mode while pattern-matching logic in the FPGA seeks to identify the pattern without error over a certain number of repetitions. If any errors are caught, ps-resolution adjustments are made to delay elements either in the ADC databus, or the ADC clock until the sweet-spot is found in the data-valid window. The adjustable delay elements can be either iDelay primitives in the IOB of 7-series / Zynq or delay elements in the ADC itself (ad9643). This technique can automatically compensate for any skew on the ADC databus from trace length mismatch, and frees the design from IO constraints which become irrelevant, since the clock-to-data relationship is dynamic. Both the above reference designs use these techniques, depending on whether you prefer to implement the ADC calibration using a hardware-based state machine (www.em.avnet.com/k7dspkit), or under software control (www.em.avnet.com/adizynqsdr).
 
If your ADC does meet this criteria we can discuss clocking, but it may also depend on what your application intends to do with the data within the FPGA fabric. Assuming the data can be captured error-free into the 1st synchronous element in the IOB, you will probably not be able to route full speed 500 MHZ data very far through the fabric of the MicroZed Zynq device without decimation of some sort.
 
If your ADC and application do fit these parameters the MicroZed FMC carrier might be the best way to prototype and test your design: http://zedboard.org/product/microzed-fmc-carrier
 
-Gary

smvo555's picture
smvo555
Junior(0)
interesting..

Hi Gary,

Thank you for your response, I appologize it took so long for me to get get back to you on this, but I didn't think any body responded to my question. (no email notification) I've been very busy with a different project latelly, and am now having more time to get back to the micro zed development. Since my original post of this question we've had interface pcb's made to connect the ADC(AD9434) to the uZed carrier which I will be getting around to testing within the next couple of weeks. Let me digest your response please and I'll post later with an update on this.

-Sam

TroutChaser's picture
TroutChaser
Moderator(18)
You can subscribe to the thread

If you click the 'subscribe' link right below your original post you can setup a notification that a comment has been added to this thread.
 
-Gary