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UART0 routed through PL - Rx not working

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Ango42's picture
Ango42
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UART0 routed through PL - Rx not working

Hi,
I routed the UART0 signals of the zynq available on the picozed board through the PL and make them externals to shift signals level to 3V3. 
On the PS side, I have a linux environment (4.4.0) generated with Yocto.
The UART1 is already used for the console and it is working perfectly. I would like to use UART0 for a custom application, but the Rx signal is not working.
First to check if the UART0 is working correctly I connected the RX and TX signals of UART0 to a 3V3 FTDI USB cable which is connected to my laptop.
After setting a correct configuration of the serial communication (115200, 8, 1, no parity) I used the following command to send a message to my laptop : 

echo "HelloWorld" > /dev/ttyPS0
And I received the following message on my computer (using putty) : 

HelloWorld
So the Tx signal of UART0 is working.
Then to check the RX signals I performed a similar operation and used the following command to read data : 

cat /dev/ttyPS0
This command is waiting for data.
On my laptop I enter any characters but I never received any data on the picozed board.
To check if the signal is routed correctly I double check the pinning in my vivado project and add an ILA to see RX signals in the chipscope.
When data are available I can see them in the chipscope and I can say that it isn't an hardware issue.
For both UART0 and UART1 the uartps driver is used and seems to work correctly for UART1. I don't understant why it is not working for UART0. 
Tx is working but not RX so I think about interruptions. To see any interruption, I see the /proc/interrupts file and have the following : 

           CPU0       CPU1

 16:          0          0       GIC  27 Edge      gt

 17:          0          0       GIC  43 Level     ttc_clockevent

 18:     599772     119714       GIC  29 Edge      twd

142:          1          0       GIC  57 Level     cdns-i2c

143:         20          0       GIC  80 Level     cdns-i2c

145:          0          0       GIC  35 Level     f800c000.ocmc

146:          1          0       GIC  59 Level

147:          3          0       GIC  82 Level

148:         26          0       GIC  58 Level     e0006000.spi

149:          2          0       GIC  81 Level     e0007000.spi

150:       2064          0       GIC  51 Level     e000d000.spi

151:      32639          0       GIC  54 Level     eth0

152:       7111          0       GIC  79 Level     mmc0

153:          0          0       GIC  45 Level     f8003000.dmac

154:          0          0       GIC  46 Level     f8003000.dmac

155:          0          0       GIC  47 Level     f8003000.dmac

156:          0          0       GIC  48 Level     f8003000.dmac

157:          0          0       GIC  49 Level     f8003000.dmac

158:          0          0       GIC  72 Level     f8003000.dmac

159:          0          0       GIC  73 Level     f8003000.dmac

160:          0          0       GIC  74 Level     f8003000.dmac

161:          0          0       GIC  75 Level     f8003000.dmac

162:          0          0       GIC  40 Level     f8007000.devcfg

171:          0          0       GIC  68 Level     xilinx-vdma-controller

IPI1:          0          0  Timer broadcast interrupts

IPI2:       8754      10100  Rescheduling interrupts

IPI3:          0          0  Function call interrupts

IPI4:         24         18  Single function call interrupts

IPI5:          0          0  CPU stop interrupts

IPI6:          1          0  IRQ work interrupts

IPI7:          0          0  completion interrupts

Err:          0

 
IRQ 59 and 82 are used for UART0 and 1 but not listed for uartps (yesterday it was listed only for IRQ 82).
To check if the configuration is well done on the UART0 I used the utils devmem2 to read and write UART Controller Registers (Appendix B.33 ug585). I found out that UART0 is not configured like UART1. But when I try to change its settings, nothing happens and I can't receive any data.
Thanks for your help.