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Ubuntu Server on UltraZed

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tchoyt's picture
tchoyt
Junior(2)
Ubuntu Server on UltraZed

I've written up a guide on getting the UltraZed starter kit up and running on Ubuntu Server 16.04.2.  
There's no display port interface - just serial console and ethernet connectivity.  The included base design is very simple - just a ZynqMP PS with LED's and a block RAM.  
 
Please read the issues section at the bottom of the blog post as there area ALOT of things that don't work properly with the Xilinx 2016.4 release.  
 
The intent here is to use the associated github repo as a framework for getting your own custom design up and running on Linux.  
 
Blog Post:
http://www.twosixlabs.com/ubuntu-on-ultrazed-embedded-high-performance-c...
 
Github Repo:
https://github.com/invincealabs/ultrazed_dev
 
EDIT:  We're in the middle of a company re-branding right now so the blog post has moved to our new website.  The github is currently still under Invincea Labs

zedman2000's picture
zedman2000
Moderator(2)
HI there,

HI there,

Thanks for the awesome write up using UltraZed!
It seems pretty detailed and step-by-step!
I'm going to ensure this gets stickied to help out the rest of the UltraZed community!

--Dan

tchoyt's picture
tchoyt
Junior(2)
Updated to Xilinx 2017.1 Release

I've updated the Ubuntu on UltraZed design to the 2017.1 tools.  Pretty much all of the stability issues have been resolved so it's a very usable system at this point.
Requirements:
Vivado 2017.1, Xilinx SDK 2017.1 and Petalinx 2017.1
​Updates: 
Petalinx 2017.1 is now used to build uBoot, ATF and the Linux kernel.
The FSBL is ran on the RPU in lock-step mode.
I've added a dummy AXI4-Lite register block to use as a starting point for interfacing to custom FPGA logic as well as a heartbeat LED.
Blog Post/User Guide:
https://www.invincealabs.com/blog/2017/03/ubuntu-ultrazed/
 
Github Repo:
https://github.com/invincealabs/ultrazed_dev

tchoyt's picture
tchoyt
Junior(2)
I/O Breakout Board Jumpers

I was contacted by another engineer using the blog post and github repo to develop on the UltraZed who was experiencing a failure to boot that seemed to be a result of the clock generator jumpers being installed incorrectly.  The FSBL and uBoot would come up and then would stall when booting the kernel.  
 
The 2017.1 update seems to disable the PS-PL reference clocks during the boot process, possibly in the PMU firmware to save power?  To work around this issue I now use the PL reference clock from the I/O breakout boards clock generator as a reference for the FPGA logic and the AXI HPM0 interface.  It's possible without this clock present the AXI interface could cause the kernel to fail to boot?
 
The correct jumper locations are:  JP1 - OPEN,  J1- 1-2, J2 - 1-2

tchoyt's picture
tchoyt
Junior(2)
2017.3.1 + Petalinux + Production Silicon

The repo has been updated to the 2017.3 tools and I'm now using Petalinux to build the Linux kernel, uBoot, device tree, FSBL and PMU firmware.  I'm still lagging behind updating the blog post but you *should* be able to use the 'build_all.sh' script to build everything.
 
Stay tuned for a FreeRTOShellow world application running alongside Ubuntu on on the RPU
 
Blog Post:
https://www.twosixlabs.com/ubuntu-on-ultrazed-embedded-high-performance-...
 

GitHub Repo:
https://github.com/twosixlabs/ultrazed_dev
 

zjeng's picture
zjeng
Junior(1)
ES1 or production silicon

Hi, super job!
Do this build still address ES1 silicon?
Any clue what to change to use production silicon?

tchoyt's picture
tchoyt
Junior(2)
Hi,  Sorry it wasn't that

Hi,  Sorry it wasn't that clear in my post, this update is targeting the production silicon using the free webpack Vivado tools.
 
I have verified that an FPGA image built against the production parts will configure and operate just fine in ES1 silicon so you should be fine using the ES Ultrazed starter kits.