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UltraZed-EG SoM PL BRAM access from PS.

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UltraZed-EG SoM PL BRAM access from PS.


Our PL has 8KB BRAM.  BRAM's primary purpose is to exchange data between PL-PS. The APU (A53) hosts a RTOS, and one of the processes needs to access this BRAM. We mmap the entire BRAM in RTOS APU driver, which makes it available to the client process.  Caching has been disabled on mapped BRAM. BRAM dataword is 16-bytes wide. 


Issue: As a test run, we write (byte sized granularity) to BRAM from PS and read-back to compare the data.  It seems that stale data from previous write is read-back. 


What could possible cause such issue? And, do we need to do anything specific on this platform to ensure cache coherency?






Well, it depends. It depends on what your pipeline looks like and what you are wrapping around the BRAM. If you are not using built in IP, I would highly suggest it. You can use an AXI BRAM that is FIFO based. This would let you control what data goes where, have watermarks for data fill levels and more. It consumes a bit more logic, but I believe it would be worth it to really let you see what is going on in the data.

Doing this also allows you to better control the dual port memory and who is writing when.

The data might also be stale as it takes time to get the data into the BRAM and if you are reading OUT before the data has flushed to the front you will read old data. If you look at documentation on how BRAM works, you will likely see what I am referring to.