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VHDL instantiation file for PS in Vivado

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4 posts / 0 new
Viterbi's picture
Viterbi
Junior(0)
VHDL instantiation file for PS in Vivado

hello,

I am trying to find a way of generating the VHDL instantiation file for my processor system in ZedBoard. So far I have only been able to generate it in Verilog... there is some options that says "file type" but nothing happens if you change it to VHDL. How is one supposed to get the component instance in VHDl?¿!

Thanks!

rlewis65's picture
rlewis65
Junior(0)
Same issue

I've raised a webcase with Xilinx to report this issue. However the person assigned to the case is claiming he can't reproduce the issue. I'm pulling my hair out since the project setting is definitely VHDL. Other IP are instantiating in VHDL just not the PS

Viterbi's picture
Viterbi
Junior(0)
Wow.... that definately sucks

Wow.... that definately sucks.... Is there anyway I can help? Maybe it has something to do with chossing the default template for ZedBoard when creating a project.. I don't know... Let me know if there is anything I can do to help...
Also, if you could post any news about the topic that would also be good ;)

rlewis65's picture
rlewis65
Junior(0)
Xilinx confirms this is an issue

Xilinx support have been able to reproduce and have submitted it to the development team for a possible fix. The support guy actually said to me: "Do you really need to use VHDL?" Hmmmm.... For now I am using PlanAhead. Vivado is too broken. Also need and EA license to use the IP integrator. So even if the top level is constructed there is still an issue exporting to the SDK.