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Vivado 2013.1

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LarryQW's picture
LarryQW
Junior(0)
Vivado 2013.1

The new Vivado 2013.1 just came out. It's supposed to have better integration with Zynq.

I've got parts to work, but not all. Anyone worked through the new Vivado 2013.1 design tool for the zedboard yet?

After getting it to install (by installing the "Vivado System Edition", not webpack edition, then use the webpack license) I find I can indeed add a Zynq through the IP catalog rather than opening XPS (which no longer exists). I can also configure the PS same as before in XPS, and Vivado even has a Zedboard template for the PS configuration.

However, the UCF files are no longer supported. I've tried to use some of the other formats by porting from a pre-existing ISE 14.4 project, but no success so far. I'm getting failure from 130% I/O utilization.

Anyone worked through the new Vivado 2013.1 design tool for the zedboard yet?

TTEMSK's picture
TTEMSK
Junior(0)
An interesting hack to use

An interesting hack to use the System edition with the Webpack license. Judging from the info in the Xilinx download page the Webpack seems to be targeted for Artix and Kintex only, not ZYNQ.I'm wondering if your hack really can circumvent that limitation - although your symptoms sound like it might.
Rgrds, Mikko

TTEMSK's picture
TTEMSK
Junior(0)
Is ZYNQ supported or not?

It's funny, actually. The download page http://www.xilinx.com/products/design_tools/vivado/vivado-webpack.htm says "Vivado Design Suite WebPACK Edition supports the Artix™-7 (7A100T, 7A200T) and Kintex™-7 (7K70T, 7K160T) devices. Download Vivado WebPACK Now!". No ZYNQ mentioned.

But in the Release Notes http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug97... , the Architecture Support table (page 17) lists " Zynq-7000 Device (Early Access) • XC7Z010, XC7Z020, XC7Z030" under the column labelled Vivado WebPACK Tool.

LarryQW's picture
LarryQW
Junior(0)
Need Special Permission

My understanding now is that it's only possible for Vivado 2013.1 to properly program Zynq if you have a special Early Access permission for the IP Integrator.

I talked with my Avnet Field Application Engineer about getting a Early Access. He said that Vivado is not yet fully qualified for Zynq. It's more oriented now for using in programming the other FPGA chips (Virtex, Kintex, Artix). So anyone trying to program Zynq using Early Access should first be fully experienced with the Zynq and the ISE tools. Even then, he said it will be rough going.

My Avnet FAE suggested I go back to ISE 14.4 and wait for the next version of Vivado. That's what I did. I uninstalled Vivado and am working fine again with ISE 14.4 in spite of it's problems, which I know how to get around.

rlewis65's picture
rlewis65
Junior(0)
Planahead seems to be a reasonable alternative

I've had reasonable success with PlanAhead 14.5 and the workflow is similar to Vivado. However I'm having issues in the XSDK itself with compiling the board support package. It will sometimes compile which is frustrating since I hate it when software is non-deterministic.

I suppose reality is that only the ISE is sufficient for now

rlewis65's picture
rlewis65
Junior(0)
UCF can be converted to XDC with PlanAhead

Assuming your project was originally an ISE project you can generate the XDC by using the command "write_xdc filename.xdc" in the TCL command window.

rlewis65's picture
rlewis65
Junior(0)
Can also create an empty PlanAhead project

Alternatively you can create an empty PlanAhead project with just the UCF and then use PlanAhead to create the XDC file.

LarryQW's picture
LarryQW
Junior(0)
Not sure how

I tried to copy a previous xdc file from when I did the same configuration with ISE 14.4. That's when I got all the the I/O utilization errors mentioned above.

I'm not sure how to do an empty PlanAhead with just the UCF. I did't see an option for UCF entry anywhere in the new Vivaldo 2013.1.

LarryQW's picture
LarryQW
Junior(0)
Found Existing XDC file

I found an existing xdc file in a previous ISE 14.4 project. I was able to import it into Vivado and got to complaints. But later implementation complained that it needed 130% I/O resources using this file.

Maybe I need to use the "write_xdc" command instead of the existing xdc file. But I've now decided Vivado 13.1 is just not ready (see my other response) and uninstalled it.

I'm curious if anyone has been successful in configuring the Zynq or Zedboard with Vivado 2013.1.

LarryQW's picture
LarryQW
Junior(0)
typo

I meant importing the found xdc file into Vivado 2013.1 "got no complaints" at the start, only later.

rlewis65's picture
rlewis65
Junior(0)
Vivado 2013.1 and Zedboard

I've been successful in converting most ISE project to Vivado targeting Zedboard. The only snag was having to manually specify the IOSTANDARD for each pin in XDC file since DEFAULT is no longer allowed unless one disables the warning

LarryQW's picture
LarryQW
Junior(0)
What projects and license?

Were these converted projects using both PS and PL?

Did you need the Early Adopter license?

Thanks

babaraw's picture
babaraw
Junior(0)
Vivado 2013.1 and Zedboard

Hi,
Have you worked with custom peripheral in Vivado. I am working on this using IP Packag
"Before I was using custom peripheral in Planahead with my own modules integrated and everything was working perfect. Now I Just imported custom peripheral files and created an IP using Vivado IP Package. I am debugging it using logic analyzer. My writes in Custom peripheral are successful with proper response from AXI write response channel. But when I am trying to read values from custom peripheral registers Processing System is not asserting the ARVALID???. "

rlewis65's picture
rlewis65
Junior(0)
Webpack and Zynqboard Licenses

Sigh, only PL. I've since download the separate SDK package for Vivado 2013.1 but have struggled with it. In essence running into the same problem of over utilization of IO. Have you been able to work around this yet?

I've abandoned Vivado and I am using Planahead 14.5, however there are problems with this as well.

LarryQW's picture
LarryQW
Junior(0)
Given Up - Back to ISE 14.4

I gave up on Vivado 2013.1 a week ago. Went back to ISE 14.4 now.

I tried going to the new Vivado because of the flaky operation of ISE 14.4. But all three PS&PL projects I finally got working before in ISE 14.4 still compile and work properly. So I'll stick with it until Vivado 2013.2 comes out, as my Avnet FAE strongly suggested.

Viterbi's picture
Viterbi
Junior(0)
130% utilitzation

I am pretty sure this is due to the AXI_GP0 port beeing enabled in the PS and routed to IO pins, if you re-customize your PS and disable that port I think you should not get that error any more.

I have a thread about this but does anybody know how to get the PS instance template in VHDL and not Verilog??¿?¿! What XIlinx decided everybody has to use Verilog now?

rlewis65's picture
rlewis65
Junior(0)
Same issue with Verilog

I raised a webcase with Xilinx and they told me I was imagining it. Cannot get the PS template to generate VHDL even though my project settings are correct

babaraw's picture
babaraw
Junior(0)
Zynq Custom Peripheral in Vavado

Hi Gyus,
I am using Vivado 2013.1. Before I was using custom peripheral in Planahead with my own modules integrated and everything was working perfect. Now I Just imported custom peripheral files and created an IP using Vivado IP Package. I am debugging it using logic analyzer. My writes in Custom peripheral are successful with proper response from AXI write response channel. But when I am trying to read values from custom peripheral registers Processing System is not asserting the ARVALID???. Anyone who has faced this kind of problem or worked with Custom Peripheral in Vivado. Need help!
Thanks in advance.