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Vivado 2015.2 processing_system_7_0 PL fabric clock settings not setting zynq registers correctly in .bit file

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jbattles's picture
jbattles
Junior(0)
Vivado 2015.2 processing_system_7_0 PL fabric clock settings not setting zynq registers correctly in .bit file

Whenever I change the PL Fabric clock frequencies in the ZNQ7 Processsing System (5.5) GUI and then create the *.bit file the FPGA*_CLK_CTRL register have the wrong values in them. The registers either contain the default values or some of the set values, but in the wrong clock registers.

The BD where the PS7 core is instantiated is called cpu_core:

I've looked at the *.srcs/bd/cpu_core/cpu_core_processing_system7_0_1 directory. All the config files have the correct divisor 0 and frequencies set in them. The includes the ps7_* files, *.xci, *.xdc, *.xml

However, once the bit file is generated, converted to a bin via promgen, and then the Zynq programmed via /dev/xdevcfg the FPGA?_CLK_CTRL registers have the wrong values in them.

I've tried the advanced tab and setting things there as well. The new values don't seem to propagate through to where the *.bit file sets the registers. The other PL logic seems to be working fine, it's just the FPGA fabric clock registers that seem to have the wrong values in them. I've also verified with an O-scope that the frequency of the clocks routed out to pins is wrong.

Vivado 14.x didn't seem to have this problem.

I am using a Microzed Z7010 board selected in the project. The board files were downloaded from Microzed.org and it's the 2015.x version of the files. Block automation was run after instantiating the processor core and the values were changed after it.

I am running on Ubuntu 14.04 64 bit OS. I am running Vivado 2015.2

If I manually poke the registers to the correct values, then I get the correct clock frequencies, but the values don't seem to be propagating through to the *.bit file. If I reload the bit file, the registers go back to the wrong values. So it's the way the *.bit file is being built.

I've tried clearing out all files in the build and cache directories along with deleting the core, clearing out it's IP files and re-adding and rebuilding everything. The new build only had the default GUI values in the registers after loading the *.bit file.

I have verified *.bit file are getting built new and the correct *.bit file is getting converted to a *.bin file and put on the Microzed and programmed in through xdevcfg. Since all the source files look to have the correct values in them, I believe it is a problem is the way that data gets put into the *.bit file to setup the registers somewhere along the chain that has a possible bug and is not transferring the correct values to the *.bit file. It seem like it's either partially picking up the changes or ignoring them all together.

jbattles's picture
jbattles
Junior(0)
The Vivado tool's *.bit does not set the PS registers, FSBL does

I received the following comment in the Xilinx User Forums
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rjsefton 09-01-2015 05:27 AM - edited ‎09-01-2015 05:29 AM

These clocks are generated in the PS so have nothing to do with the .bit file, which programs the PL. The information to initialize the PS clocks is carried in the .hdf file over to the SDK. You need to do a File -> Export -> Export Hardware and check the box to include the .bit file. This creates the .hdf file, which is then imported to the SDK where the FSBL (first stage boot loader) is created. It's the FSBL that initializes the PS clocks on power-up.

I'm not a software person and never use the SDK, so this may not be 100% correct. But it's generally correct. The important point is that the .bit file has no impact on the PS to PL clocks.

Make sense?
--------------------------------

I reran the PS side register poke test, then reloaded the *.bit file and the register values did not change like I had previously thought they did. So his answer looks correct.

I am still working on conceptually understanding the Zynq and how it is setup by different parts of the tools. The answer provided really helped me realize that there are two parts to this chip - the CPU system and the FPGA and even though the clock values are setup in Vivado which builds the *.bit file, they get programmed by the FSBL created by the XSDK.

TroutChaser's picture
TroutChaser
Moderator(18)
Hello John,

Hello John,
 
Your understanding is correct. You can also add a .init (register initialization file) partition to the FSBL when you generate the FSBL. The PS register values defined in this .init file will be programmed prior to execution of the FSBL user code. This method would allow you to change these register values without exporting the Vivado HW project again. You would need to modify the .init file and use the SDK to generate a new FSBL image.
 
-Gary