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Xillinux

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deaxman's picture
deaxman
Junior(0)
Xillinux

In order to use Xillinux and Xillybus to moniter registers through the linux command terminal with /dev/something what do I have to do on the FPGA side, I figure I need to add the Xillybus IP but each time I load the bit file with impact it shuts down the PS (Xillinux) side and the logo disappears. How can I load a design, (e.g. switch on --> led on is a common one) and have the terminal tell me the state of the switches? Any documentation on this or examples? I've read all of the xillinux documentation and it helped on the Xillinux side but nothing on the PL side or about creating a custom bit file and reading the registers defined in the HDL code used to create it. Thanks a ton!

eli's picture
eli
Junior(1)
Hi,

Hi,

Section 5.1 in the Xillinux guide explains how to integrate custom logic with Xillybus. To make a long story short, the boot.bin file should be generated with the new bitfile included, and then copied to the SD card (overwriting the existing one).

Loading a bitfile with Impact doesn't work, as you've noted.

Regards,
Eli

deaxman's picture
deaxman
Junior(0)
Excellent!

Great! I saw that a little while ago I think but I thought they were talking about something else since it wasn't the normal way I'm used to writing a bit file. Thanks!

deaxman's picture
deaxman
Junior(0)
xillydemo

So to do this I should modify Xillydemo.v? They say add extra hdl files but synthesis to a bit file only uses one hdl file right? So I either need to replace or change xillydemo but it has the IP connections etc in it so it seems like changing it is the only alternative? Is this true? Thanks!

eli's picture
eli
Junior(1)
Xillydemo is the top level

Xillydemo is the top level module of the entire project, and as you can see in the sources, it instantiates other modules (which are in other files).

To integrate your own logic into the project, the common way to go is adding some HDL files and instantiate your module(s) in the Xillydemo module + rewire and possibly add FIFOs as necessary. This requires some knowledge in Verilog or VHDL, or course.

The general idea is to squeeze in the application logic instead of the loopback wiring. If you bring yourself to understand how the original Xillydemo module is put together, it's hopefully obvious what to do.

Regards,
Eli

deaxman's picture
deaxman
Junior(0)
Great thanks!

Works great now, I figure I probably need to impliment a FIFO of some kind to access the registers from Xillinux through /dev

eli's picture
eli
Junior(1)
Well, sort of. If you want to

Well, sort of. If you want to access registers (i.e. reads and writes with addresses), you probably want to use something in the style of /dev/xillybus_mem_8, which has a memory access interface on the FPGA side. You may also consider using Xillybus Lite, which is also included in the Xillinux bundle

Eli

deaxman's picture
deaxman
Junior(0)
Thanks!

Thanks!