Sorry, you need to enable JavaScript to visit this website.

XPS - ERROR: Coregen did not generate file

Unsolved
10 posts / 0 new
Mangibu's picture
Mangibu
Junior(0)
XPS - ERROR: Coregen did not generate file

I followed the tutorial “ZedBoard: Zynq-7000 AP SoC Concepts, Tools,andTechniques”,
3.1.1 Take a Test Drive! Check Functionality of IP instantiated in the PL.

At step 33, when I generate the bitsteam, I get the following errors:

ERROR:EDK - chipscope_axi_monitor_0 (chipscope_axi_monitor) - ERROR: Coregen did
not generate file
"C:/MG/XProjects/ZP2/ZP2.srcs/sources_1/edk/system/implementation/chipscope_axi_monitor_0_wrapper/chipscope_axi_monitor_0.ngc"

ERROR:EDK - chipscope_icon_0 (chipscope_icon) - ERROR: Coregen did not generate
file
"C:/MG/XProjects/ZP2/ZP2.srcs/sources_1/edk/system/implementation/chipscope_icon_0_wrapper/chipscope_icon_0.ngc"

ERROR:EDK:440 - platgen failed with errors!

make: *** [implementation/system.bmm] Error 2

Could anyone help with this? I use Version 14.4.

Thank you very much.

Michael

Mangibu's picture
Mangibu
Junior(0)
summary of my license file

Thanks to everyone for helping.

Here is a summary of my license file (I have removed the VENDOR_STRING and the HOSTID):

# ----- REMOVE LINES ABOVE HERE --------------------------
#
# This license is valid from Thu Nov 01 15:56:19 GMT+00:00 2012.
#
# This is license NODELOCKED to HOSTID=000c29d19a9e;
# there is no need to run lmgrd for this license.
#
#
# This is a permanent license generated on Thu Nov 01 15:56:19 GMT+00:00 2012
INCREMENT ZEDWEBPACK_XC7Z020 xilinxd 2013.11 permanent uncounted \
D767869DBD2D \
VENDOR_STRING=
HOSTID=
#
#
# ----------------------------------------------------------------------
# The following PACKAGE definition is a REQUIRED part of this license:
#
PACKAGE ZEDWEBPACK_XC7Z020 xilinxd 2013.11 0EED433094BF \
COMPONENTS="WebPack XPS_TDP XC7Z020 ChipscopePro_TDP ISIM \
PlanAhead" OPTIONS=SUITE
#
# ------------------------------------------------------------------------------
#
# ----- REMOVE LINES BELOW HERE --------------------------

The Chipsscope license is mentioned, so it should be ok????

BTW: Always when I launch XPS I get an license error. It is not possible to launch XPS from PlanAhead by double-clicking “system_i-system(system.xmp)”. XPS will start but with an license error and the project is not open. My workaround is to open XPS for example from the windows start menu and then to open the system.xmp by “Open Project” from the “File menu”.

When I remove all Chipscope IPs I have no problems.

BTW: I am running Version 14.4 on Windows 7 Pro SP1 64-Bit.

Thanks for helping.

Michael

Mangibu's picture
Mangibu
Junior(0)
I solved the problem.

I solved the problem.
I used the WebPACK version of the tools. I uninstalled the Xilinx tools and then I installed the Logic Edition of the tools. Now everything is working fine. Also XPS is launching from PlanAhead.
Michael

yh's picture
yh
Junior(0)
Mine still cant work.

Mine still cant work.
I am using system edition.

timobility's picture
timobility
Junior(0)
Coregen issue with 14.4

Coregen issue with 14.4

It seems Xilinx has an issue with the WebPack install of 14.4. It doesn't enable coregen properly.
The answer record link is below.
I added the environment variable to my webpack install and it seems to have gotten over its coregen issues.

Managed to build the Digilent "OOB" design with this set.

http://www.xilinx.com/support/answers/53695.htm

jimmy8887's picture
jimmy8887
Junior(0)
Same problem as Mangibu

Hi,
I have the same problem as Mangibu. When I try to generate bitstream, I get the same error. I am using version 14.3 on Windows 7. Is there any other solutions?(I am using school computer, no admin rights)

the error massage is :

Generating IP...
Configuring files for chipscope_axi_monitor_0 root...
Gathering HDL files for chipscope_axi_monitor_0 root...
ERROR:EDK - chipscope_axi_monitor_0 (chipscope_axi_monitor) - ERROR: Coregen did
not generate file
"H:/4th-year-project/Zedboard/Demo2/project_1/project_1.srcs/sources_1/edk/sy
stem/implementation/chipscope_axi_monitor_0_wrapper/chipscope_axi_monitor_0.n
gc"
IPNAME:chipscope_icon INSTANCE:chipscope_icon_0 -
H:\4th-year-project\Zedboard\Demo2\project_1\project_1.srcs\sources_1\edk\system
\system.mhs line 166 - elaborating IP
Created elaborate directory hdl/elaborate/chipscope_icon_0_v1_06_a/synhdl/vhdl/
Generating ChipScope core: chipscope_icon_0 ...
ChipScope Core Generator command: coregen.exe -b
H:/4th-year-project/Zedboard/Demo2/project_1/project_1.srcs/sources_1/edk/system
/implementation/chipscope_icon_0.xco
Release 14.3 - Xilinx CORE Generator P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
All runtime messages will be recorded in
H:\4th-year-project\Zedboard\Demo2\project_1\project_1.srcs\sources_1\edk\system
\implementation\chipscope_icon_0_wrapper\coregen.log
Updating project device from '7z020' to 'xc7z020'.
Wrote CGP file for project 'coregen'.
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for chipscope_icon_0 root...
Gathering HDL files for chipscope_icon_0 root...
ERROR:EDK - chipscope_icon_0 (chipscope_icon) - ERROR: Coregen did not generate
file
"H:/4th-year-project/Zedboard/Demo2/project_1/project_1.srcs/sources_1/edk/sy
stem/implementation/chipscope_icon_0_wrapper/chipscope_icon_0.ngc"
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system_processing_system7_0_wrapper.ngc] Error 2
ERROR:EDK -
Error while running "make -f system.make netlist".
ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [H:/4th-year-project/Zedboard/Demo2/project_1/project_1.srcs/sources_1/edk/system/__xps/pa/_system_synth.tcl]

dariogomez's picture
dariogomez
Junior(0)
Also had this problem. Found a solution

I also had the same error described on this thread: ERROR:EDK - chipscope_axi_monitor_0 (chipscope_axi_monitor) - ERROR: Coregen did
not generate file ...chipscope_axi_monitor_0_wrapper/chipscope_axi_monitor_0.ngc

I found a warning on the coregen.log file inside this folder. It says:
WARNING:sim:882 - The working directory path for this project is very long (>160
characters). Generation will fail if the full path length of any generated
file exceeds MAX_PATH, i.e. the Windows NT limit of 260 characters.

Further down on that same file there are other warnings indicating "cannot open file" for file:
...chipscope_axi_monitor_0_wrapper/tmp/_cg/_bbx/chipscope_axi_monitor_0_chipscope_ila_v1_05_a_xst/chipsco
pe_ila_v1_05_a/chipscope_ila_v1_05_a.vdbl

I found that the path length for this file is 271 characters and verified that Windows 7 would not allow me to create any files with this path length.

Anyway, moving the entire project to the root (C:\) and rerunning the generate bitstream solved the problem. I am using Xilinx Ver 14.5 on Win7.

Thought I might post this here for someone else who might be having the same issue.

cjmahieu's picture
cjmahieu
Junior(0)
Moving to C:/ Drive

Can confirm dariogomez's solution of moving the project to C:/ works. (Running 14.6 system edition on Windows 7)

jerryo's picture
jerryo
Junior(0)
shorten the path

Agree that it's the shortened path in windows. Nice and direct! Thanks dariogomez.

L30nardoSV's picture
L30nardoSV
Junior(0)
confirmed solution

Yeah, I got the same error using the 14.7 embedded edition ... I've just needed to short the path!