Sorry, you need to enable JavaScript to visit this website.

ZedBoard_OOB_Design

Unsolved
3 posts / 0 new
xinxin's picture
xinxin
Junior(0)
ZedBoard_OOB_Design

ZedBoard_OOB_Design  offers us a hardware project  xps_proj.I want to design a vdma image processing .So i add xapp1167 demo's hls ip and a vdma ip  to xps_proj.But  xps can't generate system.bit     
console:xflow done!

touch __xps/system_routed

xilperl E:/ISE_14.7/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

Done! 

 

system clk1 can't meet timing    why this clk1 is 166.7mhz ??  

JFoster's picture
JFoster
Moderator(47)
Hi,

Hi,

I am going to ask that you ask your question over at the Xilinx forum as you are referencing their material.

https://forums.xilinx.com/

--Josh

xinxin's picture
xinxin
Junior(0)
Thank you!

Thank you!