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Zynq 7100 PS lockup

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billgood
Junior(0)
Zynq 7100 PS lockup

It appears that when I get to a certain utilization of the Z7100 device in the PL it will cause the PS to lockup where I cannot get access to the PS through the serial port.  I do see that the logic in the PL is still running using the Vivado Logic analyzer to probe some of the signals.  When I removed 20,000 LUTs then the issue goes away.  I did find a post that seems to be very similar issue I am having. "ps-freezes-when-making-use-pl"
 
I was wondering if there is any other information on this issue?

JFoster
Moderator(67)
Hello Billgood,

Hello Billgood,

We have not investigated this subject further, however we would like to help you solve this issue. Based on what you are experiencing, we are under the assumption that you are most likely having a power issue. Could you answer these few questions for me please.

1. What ATX power supply are you using?

2. How long ago was your board purchased?

3. Do you encounter this issue all the time? Or just sometimes? What exactly is your design doing when it happens?

4. I would suggest you scope your power rails to make sure none are dropping out, also when doing this make sure that your trigger is set to falling edge trigger to avoid missing the capture you are looking for.

--Josh

billgood
Junior(0)
Thanks for your reply I

Thanks for your reply I finally got some time to answer your questions.
1) I have tried 2 ATX power supplies.  I get the same PS lockup issue with both of them.
    a) Model: FSP300-60LG-5K (FSP Group INC)
     b) Model SPI300T8HNB (Sparkle Power INC)
2) I have 2 boards which I have tried.  The first board I received around 1 1/2 years ago.  The second board I bought about 3 months ago.  Both Mini-ITX boards have this on them "Mini-ITX-7Z-PCB-E"
3) Of the 2 boards I have tried the problem is consistent.  I have 3 builds which I have tested with.  The first build is the lowest LUT count, the second build is in the middle and the last build has the most LUTs.  The first build passed on both platforms,  the second build passed on the first platform and failed on the second platform, the third build failed on both platforms.   When the problem occurs I first power on the Mini-ITX board then load the BOOT.BIN file.  Linux loads correctly and I start the application which configures the IPs in the PL.  Once I get to the point where I start rx'ing data in the PL and DMAing it to the DDR the processor locks up. 
4) I first measured with the DMM all the voltage rails at their respective TP points 5-12 (1.5v, 1.8v, 2.0v, 3.3v, 1.0v, 1.0v_mgt, 1.2v_mgt and 2.5v).  They look good except for the 1.0v rail.  I am seeing this power rail increase in voltage.  After I power on the board and before the bit file is loaded I measure 1.036v,  After the bit file is loaded I measure 1.076v and then after I start my application which then causes the error to occur I measure 1.094v.  On the other board which seems to fail easier I measure 1.023v after power up,  after the bit file loads it is 1.047v, and after the error occurs it measures 1.084v.   I then looked at the 1.0v rail on the oscilloscope and I see  the 1.0v rail increase during the time I receive data and send it to DDR and then once the data stops the voltage goes down until the next burst of data is received.  This voltage change occurs when I have a good build with lower LUT count in it or with the higher LUT count build.  The voltage fluctuations seems to be worst with the higher LUT count builds that fail.  Looking at the Zynq 7000 electrical spec the recommended operating conditions are from .95v to 1.05v so it is exceeding those recommendations.

JFoster
Moderator(67)
Hello Billgood,

Hello Billgood,

Thanks for getting that information. I have two more questions for you.

1. Would you be willing to send me your design so I could test it out and verify the issue?

2. Are you currently in communication with your local Avnet FAE on this issue?

--Josh

billgood
Junior(0)
I can't send you the build

I can't send you the build due to confidentiality reason.
I have not talked to the Avnet FAE but I have talked to the Xilinx FAE.

JFoster
Moderator(67)
Hello Billgood,

Hello Billgood,

I would like to take this converstation off of the public forum, please refer to your private messages located on the top right corner of the webpage.

Thanks,

Josh

dmitrik
Junior(0)
Same problem here

Hello,
 
I believe I'm hitting the same problem. Is there any progress?
 
In my case I have a design using large amount of resources (DSPs and BRAMs) and all 4 AXI-HP channels. The design meets timing at 200Mhz.
The software is a very simple bare-metal app. It just sets bit in register to start operation and  waits for completion. I've added code to reprogram FPGA clock divisor value in software.
At 50Mhz or 66Mhz everything works fine.
At 100Mhz I start seeing occasional random glitches in the data, located mostly towards the end of computation.
At 200Mhz the PS either locks up or dies completely, dropping JTAG connection.
While investigating the issue I set a pair of HW breakpoints, just before and just after writing '1' to register to start the operation. When (if) it stops at the second breakpoint I see the entire content of memory suddenly changing and it appears that entire memory subsystem is stuffed up, for example writing to memory using "mwr" in XSCT console has no effect or causes random changes in wrong memory locations(!).
I do have AXI protocol checkers and  chipscope connected to all AXI busses and everything looks OK on the PL side (when it works).
 
I now strongly suspect it being a power supply issue. I see these kinds of spikes on the power supply voltage (that's running a 66Mhz or 3 times slower than the target):

[ Inserting picture does not seem to work, image url is: https://preview.ibb.co/maTUhR/power.png ]
 
I appreciate any help,
Regards,
Dmitri

JFoster
Moderator(67)
Hello Dmitri,

Hello Dmitri,

Could you supply the same information?

1. What ATX power supply are you using?

2. How long ago was your board purchased?

3. Do you encounter this issue all the time? Or just sometimes? What exactly is your design doing when it happens?

4. I would suggest you scope your power rails to make sure none are dropping out, also when doing this make sure that your trigger is set to falling edge trigger to avoid missing the capture you are looking for.

5. Would you be willing to send me your design so I could test it out and verify the issue?

6. Are you currently in communication with your local Avnet FAE on this issue?

Thanks,

Josh

dmitrik
Junior(0)
PM sent.

PM sent.