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Zynq memory architecture

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Zynq memory architecture

I am new to the Zynq world but now have a zedboard and am working on a new measurement product. The goal is to develop the framework of the new measurement product around the zedboard and then leverage that design into a customized design. Because I have not worked with the Zynq nor other SOC devices, I am lacking sufficient experience to make some key architectural decisions.
Design challenge/goal:
The new design will have several measurement pumps that operate in the Zynq PL fabric. These pumps can be viewed as outputting a small fixed number of samples at either streaming periodic rate or a gated rate. The number of 32-bit samples can vary between two and 16 words so these “chunks” could be treated as packets. Each measurement pump source wants to write its data into different areas of the zedboard’s DDR3 memory. Ideally the software would set-up the base DDR3 memory where each PL measurement pump would deposit its samples with as little software intervention as possible.
IN addition, the PL fabric will contain some measurement sequencer engines that will require data to be read sequentially from DDR3 memory simultaneously. I expect that the PL will read-ahead chunks of data into a FIFO so that the PL fabric can read from the PL side of the FIFO as required and thereby reducing the number of block read accesses to DDR3 memory.
I would like to leverage, to the maximum extent possible, the AXI4 and AXI4-lite EDK peripheral IP and the AXI4 interconnects, especially to the slave HP interconnect to the Zynq PS memory controller, to accomplish this task.
Review of existing designs:
So far, I have reviewed the following but probably have not fully appreciated some of the design subtleties as I am a novice in this arena.
• Zynq-7000 EPP ZC702 Base Targeted Reference Design (U925, v1.0)
• PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC (XAPP1082 v1.0)
• LogiCORE IP AXI DMA v6.03a (PG021)
• Zynq-7000 All Programmable SoC: Concepts, Tools, and Techniques (CTT) (UG873, v14.2)
• LogiCORE IP AXI4-Stream FIFO v3.00a (PG080)

From my review, it appeared that the Base TRD design shown in UG925 was similar to my application but that the VDMA was more specific to video framing and memory arrangement and may complicate memory access.

Draft Proposed Design:
My current thought is to instantiate the AXI-DMA controller and one or more AXI-4 Stream FIFO cores. My understanding is that each stream FIFO core could interface with in the PL fabric to a module that provides some level of packetization of the data coming from each measurement pump and that the combination ofd the DMA controller and the stream-FIFO would allow my samples (packets) to be placed into DDR3 memory. It is not clear to me if I need to or should use multiple stream FIFO cores or if a single core with an appropriate interface module of my design can aggregate and packetize data from multiple measurement pumps. My concern is that I ideally want the data associated from a given measurement pump to be placed sequentially in DDR3 memory so that data from different pumps reside offset form different base addresses and not interleaved in DDR3 memory.

I would greatly appreciate any comments, suggestions or insights that will help me accomplish this design with the minimum of new HDL.