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Zynq Pins - Deep Dive


How to understand Zynq Pins! WooHoo!

A good question came up on the forums today by user atkarapa asking about MIO pins on the Zynq-7000.  So let's take a little bit of time going through what pins map to where, and get familiar with the naming schema that Xilinx uses for it's pins.
There are a few resources you should be looking at when referencing pin-outs for the Zynq-7000 AP SoC:
 UG865 - Zynq-7000 All Programmable SoC Packaging and Pinout (Advanced Product Specification)
This document outlines a number of things about both the Zynq-7000 AP SoC packages as well as pinouts.  It includes Pin definitions, Bank information, Mechanical drawings, Pin layout, and other details about interfacing to Zynq-7000.
Page 19 within UG865 references the ASCII pin-out files.  These files list, in a simple to read ASCII file format, all of the pins within the device.  These can be found here.  Let's take a moment to look at these files and see what they mean, and what information is available.  I am going to use the XC7Z020-1CLG484C device that is on the Zedboard, which can be found here.
First, let's look at what the columns are telling us.


This column is the actual label of the pin on the Zynq device.  These pins get their name because the grid has letters down one side, and numbers across the top.  You can see this layout on page 30 of the UG865 document.  More on reading that diagram in a few.

Pin Name

This is the name of the pin, which at times can still be cryptic, but provides more information than the pin label.  Let's take a look at the nomenclature that Xilinx uses for their pin names.

PL Pin Deffintions


There are a number of reserved special purpose pins within Zynq (and most Xilinx FPGA's) which I will review after this section.  The first general purpose IO pin available is V10 - I0_L1P_T0_13.  Let's take a look at that one.  We will break it apart on the underscores (_).
This is telling us that the pin supports both input, as well as output functionality.  Xilinx sometimes has input-only pins, so keep an eye out for those.
Zynq-7000 AP SoC (as well as all 7-Series devices) have the ability to interface to differential signals.  Differential signals are pretty slick for a lot of reasons including noise immunity, speed, and reliability.  You can read more on differential signaling here.
Differential signaling requires a Positive and a Negative signal to work properly.  On this pin, we see the P at the end of it, this is the Positive input.  There is a complementary pin with L1N in the second section of it's name.  The first part, L1, is telling us that this is differential pair 1.  If you look back at the ASCII text document, you will see there are  24 pairs in this Bank ( more on banks at the end of this signal description).
This next part is in reference to memory controllers.  The 7-Series devices have soft IP (Intellectual Property) memory controllers for interfacing to a variety of memory devices.  They do, however, rely on primitives within the IO structures and thus must be placed in certain places within a bank.
This last portion of the signal refers to the IO Bank the pin is on (see, I told you I would get to explaining banks!).  In the Zynq-7000 AP SoC, as well as in most Xilinx FPGA's including all of the 7-Series devices, breaks IO signals into Banks.  These banks of IO is how signals from the outside world get into the FPGA fabric, as well as the PS (processing system) portion of Zynq-7000.  There are several best practices associated with picking pins, however a good general rule is to keep signals that are going the to the same logic within the FPGA on the same bank.
So that is the breakdown of a "typical" signal on the Zynq device.  You will, however, notice that there are a number of signals listed within our ASCII file that do not look like this.  Here is the general naming scheme:
<Input/Output Definition>_<Differential Pair Number and Polarity>_<Memory Byte Number>_<Special Function>_<Bank Number>
We have reviewed all of those sections except for the "Special Function" part.  Here is a list of all of the special function pins on the 7020 device.  Note: pins can have more than one special function and will simply be concatinated together with underscores (_).
DQS is used by the memory controller.  This is the Data Strobe signal that is asserted whenever a read or a write to DDR memory is performed.  Think of this as the data enable signal.
DDR memory requires a reference voltage set to half of it's supply voltage for use while calibrating to ensure data transmission.  This pins is used to set that 1/2 VDD voltage.
I grouped these together because they are similar.  SRCC stands for Single Region Clock Capable, and MRCC stands for Multi Region Clock Capable.  FOr those familiar with previous Xilinx FPGA families these are similar to the GCLK pins.  For those who are not familiar these pins are used for bring clocks in and out of the FPGA.  These pins are dedicated resources that reduce clock skew and jitter.  If you are clocking something out of the fabric, or reading something in with a reference clock, you want to put the clock on an SRCC or MRCC pin.  Take a look a the clocking guide to find out more about which each of these do.
The PUDC_B pin is used to tell the FPGA what state all of the IO pins should be in on power-up.  Per this AR (answer record), if the pin is pulled low then all pins will be pulled high.  If pulled high, then all pins will effectively be floating and external loading will dictate their state.
Now we're getting into the really cool stuff.  These are the XADC input's to the AMS (Analog Mixed Signal) portion of Zynq-7000.  These pins are named where # is a number from 0 to 15 and a pin will be either P or N, never both.  These are 32 single ended, or 16 differential inputs to the AMS inputs that can be digitized by the XADC and read into the PL (and thusly into the PS).  So awesome.

PS Pin Deffinitions


Ok, now that we understand our basic PL input and output pins, we can move onto our PS pins.  All PS pins start with PS (well would you look at that ...).  The PS pins have this naming sheme:
PS_<MIO Number, Function, or Special Feature>_<Bank Number>
The primary input clock for the PS system.
This can be used as a the VREF for the DDR for the PS.
MIO are the available pool of IO pins the PS peripherals can map too.  There is a large mux that allows for different PS peripherals to map to different MIO pins.  The nomenclature here is simply just MIO#, where # is 0 to 53.  These assignments are set within the EDK GUI.
This is the reset for the PS.  This is brought out to a button on the Zedboard.  This is used to reset the processor core(s).
There are a great deal of DDR signals used by the PS on Zynq-7000.  I am not going to go into all of them here, but there are control signals, data lines, and address lines used.  They all are well labeled with respect to how the industry labels the same pins on their memory devices.

Reserved Pin Definitions


Ok, now we have gone over the PL and PS pin definitions and their special features.  Last but not least there are our special reserved pins all within Bank 0.
This is the reference ground, and reference power supply for the XADC within the AMS system.
This is the input threshold voltage for Bank 0.
This is the Decrypter battery supply voltage.  If you are not using the decrypter you can safely pull this to GND.
These are temp-sensing diode pins.  This diode access can be used to monitor temperature, although per UG865 you should use the temp sensor within the XADC rather than this diode.
This is the posstive and negative analog inputs that make up the 17th input to the XADC.
These are dedicated pins.  RSVDGND must be pulled to GND, and RSVDVCC[3:1] must be pulled to VCCO_0 (Bank 0 voltage).
This pin dictates what voltage the configuration bank (Bank 0) will run at.  If pulled high it will be 3.3V/2.5V operation, or if pulled low it will be 1.8V operation (which is nice for low power applications).
These signals are used while programming the FPGA.
These signals make up the JTAG interface.  JTAG is a boundary scan technology that allows for the FPGA to be programmed and interfaced it.
So is your head spinning yet?  Don't get overwhelmed!  As you are doing your design just take each pin at a time and use the above as a reference to better understand which each pin means.  Now back to our column definitions (I bet you forgot we were doing that didn't you ...).

Memory Byte Group

This is a nice way to quickly see what byte group a pin is in for your DDR memory interface.  More on the memory interface and MIG (Memory Interface Generator) in a latter blog post.



This it the bank number of the pin.  Bank 0 is the configuration bank, and banks that are in the 500's are PS banks.


VCCAUX Group, Super Logic Region


These don't have anything to do with the 7020, but do for other Xilinx FPGA devices.


I/O Type

There are five different types of IO:
This type is reserved for the configuration pins described above under the Reserved Pin Descriptions section.
HR stands for High Range.  These banks allow for voltages from 1.2V up to 3.3V.  These allow for a very wide input range of IO voltage which is really convenient.
HP stands for High Performance.  These IO are designed to be used with high-speed memory interfaces and other high-speed digital data transfer.  These banks only support up to 1.8V IO.
These are the configurable (Muxable) IO pins that the PS can route it's peripherals too.  There are contraints on which peripherals can go to wich pins.  Also, not all peripherals can be brought out at the same time since there are more peripherals then there are MIO pins.
These are pins that interface to the DDR memory on the PS.



This is a very important column if you are planning on migrating between the 7010 and the 7020 (or the 7030 and the 7045).  These are the pins you should not connect if you are planning on migrating, as they are not pinned out on each device.  If you are not planning on migrating to any other device, you can safely ignore this column.




Well that pretty much covers the majority of what you will come up against with understanding how Xilinx does pin naming.  Dive into UG865 to get a better idea of how these pins are laid out to the ball grid array on the IC package it's self.
Happy Zynq'ing!


Hi guys,

quick question on the fly (sorry for its simplicity): is it possible to access the MIO pins from the PL in any way? For example: an SPI Flash is connected to some MIO pins (initially considered to be accessed by the SPI controller) and is needed to be accessed by an IP core instantiated in the PL! Possible or not?

Thanks in advance!


Most of the cores route the output pins to the PL as EMIO connection. In the PL they can be connected to FPGA cores. Table 17-6 in the Zynq TRM lists the EMIO signal names.

will the MIO signal strength got reduce when it is taken to PL through EMIO

I have been told that it is not possible to access MIOs from PL. Is your hardware already developed? Do you need access to the SPI from both the PS as well as your PL IP core? Or just the PL IP core?

Is there a tool to setup the MIO mux registers?
Something where I can select a part/package then configure which pins are connected to the different IO blocks in the PS.
I have used the TI and Freescale tools. The tools are poor, but better than figuring it all out on paper.

You can do this either in ISE XPS or Vivado IPI. To see the ISE XPS flow, you could review the Zynq Intro training that we have posted. For Vivado, you could review the CTT 2013.2.

hello,I am creating memory controller on zedboard, but i just cannot choose the ddr3 pins in bank 502 when i created the MIG,that is to say, on the step:pin selection, there isn't bank 502 that can be chosen(only bank 13 33 34 35),how should i continue? thanks

If you are creating a memory controller for the PS (which is the only one that makes sense on ZedBoard), then you do not use MIG. Have you looked at the CTT or any of the introductory tutorials? In Vivado, this is done in the Zynq IP section of Block Design. If you select the ZedBoard when you create the project, then this controller gets automatically set up for you if you choose to use the presets.


While am checking the 7 series checklist thta has bee provided by the xilinx,i provide the MIO2 to MIO6 for QSPI but in the description it  is still showing as MIO pin not used.

Is it an issue or excel error.

Hi! I am using only ISE and would like to figure out a way for the programmable logic to interface with the UART. Ideally, I want a verilog module that outputs RX and inputs TX so that I can interface with the data directly. Is this possible? than you!

The version of UG865 that I have v1.8.1 on pg 13 it says that RSVDGND should be floating not pulled to GND as mentioned above.
There is a Xilinx AR70537 that warns that if you use the STARTUPE2 primative the RSVDGND pin could become an output.