- Home
- Products
- UltraZed
- Ultra96
- XRF16 RFSoC
- Zynq UltraScale+ RFSoC Dev Kit
- Zynq Mini-ITX
- Picozed
- Microzed
- MiniZed
- ZedBoard
- Accessories
- Obsolete-Families
- Applications
- Support
- Projects
This class demonstrates the hardware and software flows for creating your first Xilinx Zynq®-7000 All Programmable SoC design. Through a series of instructor presentations (based on 2013.3) and hands-on labs ( 2015.2 and 2016.2), hardware and firmware engineers will learn all the required steps for creating a Zynq-7000 All Programmable SoC design on either ZedBoard™ or MicroZed™. It covers the architecture of the ARM® Cortex™-A9 processing system (PS) and the integration of programmable logic (PL). The course also details the individual components that comprise the PS, I/O peripherals, clocking, interrupt, AXI interfaces and memory controllers. Emphasis is placed on efficient PL-to-PS interfacing including integration of custom PL-based IP. To complete the design cycle, the critical steps of hardware debugging techniques are also shown.
Pre-requisites:
Download the labs (Vivado 2015.2)
Download the labs (Vivado 2016.2)
Chapter-1 | Zynq Overview | View |
Chapter-2 | Xilinx Embedded Tool Flow | View |
Lab-1 | Building a Basic Zynq Design | |
Chapter-3 | Zynq Processor Overview | View |
Lab-2 | PS Configuration Part 1 & Hello World | |
Chapter-4 | Zynq Peripherals | View |
Lab-3 | PS Configuration Part 2 – MIO Peripherals | |
Chapter-5 | The Power of TCL | View |
Lab-4 | Using TCL in Vivado Embedded Designs | |
Chapter-6 | Adding Programmable Logic Peripherals | View |
Lab-5 | Adding a PL Peripheral | |
Chapter-7 | Zynq Processing System DMA Controller | View |
Lab-6 | Improving Data flow between PL and PS utilizing PS DMA | |
Chapter-8 | Creating Custom IP | View |
Lab-7 | Adding Custom IP to Vivado® IP Catalog | |
Chapter-9 | Vivado Hardware Manager | View |
Lab-8 | Hardware Debugging Zynq®-7000 All Programmable SoC Designs | |
Chapter-10 | Next Steps | View |