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Developing Zynq Hardware (Vivado 2017.1 and 2017.4)

In the Developing Zynq Hardware Speedway, you will be introduced to the single ARM Cortex –A9 Processor core as you explore its robust AXI peripheral set. Doing so you will utilize the Xilinx embedded systems tool set to design a Zynq AP SoC system, add Xilinx IP as well as custom IP, run software applications to test the IP, and finally Debug your embedded system.  The video presentations are based on Vivado 2017.1 and there are hands-on labs for Vivado 2017.1 and 2017.4.

Pre-requisites to working the labs:

A desktop or laptop with the Xilinx Vivado Design Suite 2017.1 or 2017.4 (WebPACK Edition), installed

Download the lab files and complete lab 0 prior to beginning the course

MiniZed development board and TE Connectivity HTU21D Pmod


Download Lab Files - Vivado 2017.1

Download Lab Files - Vivado 2017.4



Table of Contents

Chapter-1 Zynq Overview View
Chapter-2 Xilinx Embedded Tool Flow View
Lab-1 Building a Basic Zynq Design
Chapter-3 Zynq Processor Overview View
Lab-2 PS Configuration Part 1 & Hello World
Chapter-4 Zynq Peripherals View
Lab-3 PS Configuration Part 2 – MIO Peripherals
Chapter-5 The Power of TCL View
Lab-4 Using TCL in Vivado Embedded Designs
Chapter-6 Adding Programmable Logic Peripherals View
Lab-5 Adding a PL Peripheral
Chapter-7 Zynq Processing System DMA Controller View
Lab-6 Improving Data flow between PL and PS utilizing PS DMA
Chapter-8 Creating Custom IP View
Lab-7 Adding Custom IP to Vivado® IP Catalog
Chapter-9 Vivado Hardware Manager View
Lab-8 Hardware Debugging Zynq®-7000 All Programmable SoC Designs
Chapter-10 The Power of Scripting using Tcl View
Lab-9 Scripting using Tcl
Chapter-11 What's next? View