Maxim Pmod: Fresno 16-Bit High-Accuracy 0 to 10V Input Isolated Analog Front End (AFE)

 The Fresno firmware design is also developed and tested for the ZedBoard kit and targets an ARM® Cortex®-A9 processor placed inside a Xilinx Zynq system-on-chip (SoC). An AXI MAX11100 custom IP core is created for this reference design to optimize the sampling rate and the SPI timing stability.  The firmware is a working example of how to interface to the hardware, collect samples, and save them to memory. The simple process flow is shown in Figure 3. The firmware is written in C using the Xilinx SDK tool, which is based on the Eclipse open source standard. Custom Fresno-specific design functions were created utilizing the AXI MAX11100 custom IP core. The SPI clock frequency is set to 4.54MHz when a 189.4ksps sampling rate is selected. The SPI clock frequency is set to 2.5MHz for all other sampling rates.