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Zedboard Enet0 MAC peripheral speed problem: to work at 100 Mbps with a stand-alone application

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2 posts / 0 new
acortes's picture
acortes
Junior(0)
Zedboard Enet0 MAC peripheral speed problem: to work at 100 Mbps with a stand-alone application

Hi,

We want to get a lower Ethernet communication speed in the Zedboard, for example 100 Mbps.

When the communication between the external PHY and the Enet0 MAC has a rate of 1Gbps, all goes OK. However, we need to work at a low frequency, 25 MHz instead of 125 MHz in order to get the 100 Mbps rate.
We try to do that through the "peripheral tests" standalone application. Then, we configure the PHY correctly (we have seen the RX_CLK which is 25 MHz).

The speed of the MAC has configured using this function:

----------------------------------------------
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
{
u32 Reg;

Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Speed == 10) || (Speed == 100) || (Speed == 1000));

Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET);
Reg &= ~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK);

switch (Speed) {
case 10:
break;

case 100:
Reg |= XEMACPS_NWCFG_100_MASK;
break;

case 1000:
Reg |= XEMACPS_NWCFG_1000_MASK;
break;

default:
return;
}

/* Set register and return */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_NWCFG_OFFSET, Reg);
}

--------------------------------------------------

We have debugged this function and it writes the net_cfg register of the MAC peripheral in order to adjust the speed mode. The final value of the register is correct (bit10 = 0, bit0=1) to get a 100 Mbps rate. However, we don't get the expected result since the TX_CLK generated by the MAC continues being 125MHz.

Does somebody know if we have to configure something else to achieve the 100 Mbps rate?

Thank you very much in advance.

acortes's picture
acortes
Junior(0)
Solving the issue

We have solved the problem by updating the value of the SLCR register:

SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 << 20);
SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 << 8);

Now, the TX_CLK is also 25 MHz and the communication goes OK.