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Analog Devices ADV7511 HDMI Transmitter Reference Design

published by fletch on Mon, 2012-10-01 11:58

The ADV7511 is a 225 MHz High-Definition Multimedia Interface (HDMI®) transmitter. It is part of the Kintex-7 KC705, Virtex-7 VC707, Zynq ZC702 and the Zynq ZedBoard evaluation boards. This reference design provides the video and audio interface between the FPGA and ADV7511 on board. The video uses a 16bit 422 YCbCr interface and the audio uses a single bit SPDIF interface.

Project Type: 
HDL
Project Category: 
Video/Multimedia
Project URL: 
http://wiki.analog.com/resources/fpga/xilinx/kc705/adv7511?force_rev=1
Product Reference: 
ZedBoard

Comments

Submitted by rabe on Wed, 2012-11-21 20:06.

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Submitted by akanksha112 on Tue, 2012-12-04 04:19.

Hi All
I am sure someone would be able to help me with this problem. I had a tough time getting through this project.Now I am able to see the following on the Tera term set to 115200 baud rate
DDR write: started (length 633091)
DDR write: completed (total 2073600)
DDR audio write: started
DDR audio write: completed (total 34)
iic_read: addr(42) data(F0)
iic_read: addr(C8) data(02)
iic_read: addr(9E) data(17)
iic_read: addr(96) data(E4)
iic_read: addr(3E) data(40)
iic_read: addr(3D) data(10)
iic_read: addr(3C) data(00)
Generating audio clicks (press 'q' to exit).
on pressing q or for that matter even before that i do not get anything on the HDMI display.

I am unable to understand where I could be going wrong. Anyone who had successfully run this project , please help in resolving this problem.

akanksha

Submitted by westip on Mon, 2012-12-10 16:36.

while ((iic_read(0x39, 0x96, 0x00) & 0x80) != 0x80) {
delay_ms(1);
}
iic_write(0x39, 0x01, 0x00);
iic_write(0x39, 0x02, 0x18);
iic_write(0x39, 0x03, 0x00);
iic_write(0x39, 0x15, 0x01);//444.1kHz,(16,20,24 bit YCbCr 4:2:2)
iic_write(0x39, 0x16, 0xb5);//Output 4:2:2, 8 bit, Style 2, falling Edge, YCbCr
iic_write(0x39, 0x18, 0x46);//CSC Enabled, +/- 4.0, -16384 - 16380
iic_write(0x39, 0x40, 0x80);//GC Packet Enable,
iic_write(0x39, 0x41, 0x10);//Power Up
iic_write(0x39, 0x48, 0x08);
iic_write(0x39, 0x49, 0xa8);//Truncate

iic_write(0x39, 0x4c, 0x00);
iic_write(0x39, 0x55, 0x20);//YCbCr 4:2:2
iic_write(0x39, 0x56, 0x08);
iic_write(0x39, 0x96, 0x20);
iic_write(0x39, 0x98, 0x03);
iic_write(0x39, 0x99, 0x02);
iic_write(0x39, 0x9a, 0xe0);
iic_write(0x39, 0x9c, 0x30);
iic_write(0x39, 0x9d, 0x61);
iic_write(0x39, 0xa2, 0xa4);
iic_write(0x39, 0xa3, 0xa4);
iic_write(0x39, 0xa5, 0x44);
iic_write(0x39, 0xab, 0x40);
iic_write(0x39, 0xaf, 0x06);
iic_write(0x39, 0xba, 0x00);
iic_write(0x39, 0xd0, 0x3c);
iic_write(0x39, 0xd1, 0xff);
iic_write(0x39, 0xde, 0x9c);//
iic_write(0x39, 0xe0, 0xd0);
iic_write(0x39, 0xe4, 0x60);
iic_write(0x39, 0xf9, 0x00);
iic_write(0x39, 0xfa, 0x00);
iic_write(0x39, 0x17, 0x02);

iic_write(0x39, 0xd6, 0xc0);

iic_write(0x39, 0x0a, 0x10);
iic_write(0x39, 0x0b, 0x8e);
iic_write(0x39, 0x0c, 0x00);
iic_write(0x39, 0x73, 0x01);
iic_write(0x39, 0x14, 0x02);

iic_read(0x39, 0x42, 0x01);
iic_read(0x39, 0xc8, 0x01);
iic_read(0x39, 0x9e, 0x01);
iic_read(0x39, 0x96, 0x01);
iic_read(0x39, 0x3e, 0x01);
iic_read(0x39, 0x3d, 0x01);
iic_read(0x39, 0x3c, 0x01);

Xil_Out32((CFV_BASEADDR + 0x18), 0xff); // clear status
delay_ms(1);
iic_write(0x39, 0x01, 0x00);
iic_write(0x39, 0x02, 0x18);
iic_write(0x39, 0x03, 0x00);
iic_write(0x39, 0x15, 0x01);//444.1kHz,(16,20,24 bit YCbCr 4:2:2)
iic_write(0x39, 0x16, 0xb5);//Output 4:2:2, 8 bit, Style 2, falling Edge, YCbCr
iic_write(0x39, 0x18, 0x46);//CSC Enabled, +/- 4.0, -16384 - 16380
iic_write(0x39, 0x40, 0x80);//GC Packet Enable,
iic_write(0x39, 0x41, 0x10);//Power Up
iic_write(0x39, 0x48, 0x08);
iic_write(0x39, 0x49, 0xa8);//Truncate

iic_write(0x39, 0x4c, 0x00);
iic_write(0x39, 0x55, 0x20);//YCbCr 4:2:2
iic_write(0x39, 0x56, 0x08);
iic_write(0x39, 0x96, 0x20);
iic_write(0x39, 0x98, 0x03);
iic_write(0x39, 0x99, 0x02);
iic_write(0x39, 0x9a, 0xe0);
iic_write(0x39, 0x9c, 0x30);
iic_write(0x39, 0x9d, 0x61);
iic_write(0x39, 0xa2, 0xa4);
iic_write(0x39, 0xa3, 0xa4);
iic_write(0x39, 0xa5, 0x44);
iic_write(0x39, 0xab, 0x40);
iic_write(0x39, 0xaf, 0x06);
iic_write(0x39, 0xba, 0x00);
iic_write(0x39, 0xd0, 0x3c);
iic_write(0x39, 0xd1, 0xff);
iic_write(0x39, 0xde, 0x9c);//
iic_write(0x39, 0xe0, 0xd0);
iic_write(0x39, 0xe4, 0x60);
iic_write(0x39, 0xf9, 0x00);
iic_write(0x39, 0xfa, 0x00);
iic_write(0x39, 0x17, 0x02);

iic_write(0x39, 0xd6, 0xc0);

iic_write(0x39, 0x0a, 0x10);
iic_write(0x39, 0x0b, 0x8e);
iic_write(0x39, 0x0c, 0x00);
iic_write(0x39, 0x73, 0x01);
iic_write(0x39, 0x14, 0x02);

iic_read(0x39, 0x42, 0x01);
iic_read(0x39, 0xc8, 0x01);
iic_read(0x39, 0x9e, 0x01);
iic_read(0x39, 0x96, 0x01);
iic_read(0x39, 0x3e, 0x01);
iic_read(0x39, 0x3d, 0x01);
iic_read(0x39, 0x3c, 0x01);

Xil_Out32((CFV_BASEADDR + 0x18), 0xff); // clear status

Some monitor does not operating. so i implement double setting and HPD(hot plug detect) set always High.

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Submitted by grouby on Fri, 2012-12-14 09:48.

Hi akanksha,

The design worked for me with my HDMI monitor.

If I have the monitor connected, and turned on,
- I see the following output from serial console:
DDR write: started (length 633091)
DDR write: completed (total 2073600)
DDR audio write: started
DDR audio write: completed (total 34)
iic_read: addr(42) data(F0)
iic_read: addr(C8) data(02)
iic_read: addr(9E) data(17)
iic_read: addr(96) data(E4)
iic_read: addr(3E) data(40)
iic_read: addr(3D) data(10)
iic_read: addr(3C) data(00)
Generating audio clicks (press 'q' to exit).
- I see video and hear audio clicks.

If I have the monitor connected, but turned off,
- I see the following output from serial console:
DDR write: started (length 633091)
DDR write: completed (total 2073600)
DDR audio write: started
DDR audio write: completed (total 34)
iic_read: addr(42) data(D0)
iic_read: addr(C8) data(02)
iic_read: addr(9E) data(17)
iic_read: addr(96) data(E4)
iic_read: addr(3E) data(40)
iic_read: addr(3D) data(10)
iic_read: addr(3C) data(00)
Generating audio clicks (press 'q' to exit).
- I don't see video or hear audio clicks (obviously)
The same symptom may occur for a monitor that has multiple inputs, and is actively polling each input in succession. The trick in this situation is to init the ADV7511 device while the monitor is actively polling the input. One way to handle this situation is to init the ADV7511 twice, as described in westip's response (see his code exerpt).

If I don't have the monitor connected,
- I see the following output from serial console:
DDR write: started (length 633091)
DDR write: completed (total 2073600)
DDR audio write: started
DDR audio write: completed (total 34)
iic_read: addr(42) data(90)
iic_read: addr(C8) data(00)
iic_read: addr(9E) data(00)
iic_read: addr(96) data(C0)
iic_read: addr(3E) data(40)
iic_read: addr(3D) data(10)
iic_read: addr(3C) data(00)
Generating audio clicks (press 'q' to exit).

Hope this helps !

Regards,

Mario Bergeron

Submitted by sha2zed on Fri, 2012-12-28 21:04.

Hello..
I want to run ADV7511(HDMI TX) application on ZED BOARD using cf_adv7511_zed application, which provided by Xilinx only.
I got some problem to run the cf_adv7511_zed.tcl

XMD% source cf_adv7511_zed.tcl
Fpga Programming Progress .............10.........20.........30.........40.........50.........60.........70.........80.........90........Done
Successfully downloaded bit file.

JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 4ba00477 4 Cortex-A9
2 03727093 6 XC7Z020

CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........1

Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1240
ERROR: Cannot Read from target

I got error "Cannot Read from target"
Can any one help me how to run this application....

Thanks and Regards,
Shashank Chaurasia

Submitted by zml on Mon, 2012-12-31 08:03.

I've followed the tutorial in http://wiki.analog.com/resources/tools-software/linux-drivers/platforms/....

However it was not clear to me how to configure the u-boot image correctly to handle the uncompressed filesystem since the u-boot images I have are the ones from the other ZedBoard tutorials and expect a "ramdisk8M.tar.gz".

Any one who has experience with u-boot configuration may give me some help please? Thank you

Submitted by Umair.razzaq on Mon, 2013-06-24 09:31.

Hi fletch and others,

I am using the HDL reference design for Zedboard. In the design files, I can not see the platform.h that is required by cf_adv7511_zed/sw/cf_adv7511_zed.c. Can someone tell me where can I find this.

thanks
umair

Submitted by Umair.razzaq on Thu, 2013-06-27 07:37.

solved, I got it generated from a new project(Hello world) in Xilinx SDK and used the same platform files in this project.

Submitted by cwcheng on Wed, 2013-12-25 19:16.

Hello,

I'm trying the HDMI ref. design in zedboard.
I can display the image through HDMI now.
But audio click sound as demo is fail. >____<
Did someone have encountered this problem and solved??
I add one Xilinx DMA IP axi_dma for spdiftx and connect to axi_spdif_tx.
The HW design is right??
And the SW programming ???
No click sound be heard.
Help Help Help

Submitted by hsaeed on Mon, 2014-01-27 01:18.

Hello all,
I know there would be some one who can help me in solving the problem.

when i run the reference design on ZEDBoard from SDK.
I see the following output on terateam.

********************************************************************
ADI HDMI Trasmitter Application Ver R1.1.1
HDMI-TX: ADV7511 Rev 0x14
Created: Jan 24 2014 At 17:39:03
********************************************************************

To change the video resolution press:
'0' - 640x480; '1' - 800x600; '2' - 1024x768; '3' - 1280x720
'4' - 1360x768; '5' - 1600x900; '6' - 1920x1080.
Mute audio and video.
APP: Driver Enabled
HPD changed to HI
MSEN changed to LOW
A new EDID segment was read.
DVI device.
------------------------- EDID BLOCK 0 -------------------------
Edid Version 1.3
Mon Timing:
Pixel clock = 108.0 MHz
H Active = 1280
V Active = 1024
Progressive
No stereo
Separate sync = 3
+ve VSync
+ve HSync
Mon Freq:
Min V Freq = 56 Hz
Max V Freq = 85 Hz
Min H Freq = 30 KHz
Max H Freq = 81 KHz
Mon Name: 170T Digital

Mon Serial: H4URA09215

Edid extensions blocks: 0
########################### EDID END ###########################

MSEN changed to HI
APP: Changed system mode to Transmitter
Un-mute audio and video.
MSEN changed to LOW
APP: Changed system mode to Disconnected
Mute audio and video.

can any one suggest what does it mean?
how can i see some image or video?

Thanks in advance.
Regards
Hamid

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Submitted by lophope on Sat, 2015-01-31 03:49.

Hi
iic_write(u32 daddr, u32 waddr, u32 wdata)

Can someone help to explain what's the meaning of daddr,waddr, and wdata?
such as iic_write(0x39, 0x55, 0x20); // Y1Y0 (AVI InfoFrame) = YCbCr 422.

Submitted by lophope on Sat, 2015-01-31 03:54.

iic_write(u32 daddr, u32 waddr, u32 wdata)
iic_write(0x39, 0x55, 0x20); // Y1Y0 (AVI InfoFrame) = YCbCr 422.
Where can I find the IIC register definition ?
I don't know why it will be YCbCr? Can someone help me ?Thanks!

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