Sorry, you need to enable JavaScript to visit this website.

XYLON Image Signal Processing (ISP) Pipeline for EMBV and PYTHON-1300-C

Xylon's logiISP Image Signal Processing (ISP) Pipeline IP core is a full high-definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in smarter vision embedded designs based on Xilinx® Zynq®-7000 AP SoC and 7 Series FPGA devices. Required hardware includes : MicroZed Embedded Vision Carrier Card, MicroZed 7020 SOM, PYTHON-1300-C Camera Module.

Project Type: 
Hardware - FMC
Project Category: 
Video/Multimedia
Product Reference: 
ON PYTHON-1300-C Camera Module