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Zed Tutorial using 14.3

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RNPittman03's picture
RNPittman03
Junior(0)
Zed Tutorial using 14.3

I am attempting to follow the tutorial from this site using the 14.3 tools release. On the second lab using the GPIO and timer on the AXI bus, I encounter a problem setting up the GPIO.

In step 20, you are supposed to be able to check a box in the '32b GP AXI Master Ports' dialog to 'Enable GPIO on EMIO Interface'. This check box is not there and is replaced with a '0' I cannot edit. A pop up explains this is autocalculated by XPS and cannot be edited by the user.

Is there another way to set this parameter so I can proceed with the tutorial?

mikaczma's picture
mikaczma
Junior(0)
Hi,

you have to change GPIO settings in I/O Peripherials Block in Zynq tab (System Assembly View). Tick EMIO GPIO in GPIO settings and set width of EMIO GPIO bus.

I hope that it will be helpful.
mikaczma

RNPittman03's picture
RNPittman03
Junior(0)
Thanks.

Yeah that did it. Thanks. :)

umaair_653's picture
umaair_653
Junior(0)
thanks from my side also :)

thanks from my side also :)

wk.open's picture
wk.open
Junior(0)
No 'Enable GPIO on EMIO Interface' option

Hi I'm doing the same tutorial also. But in my XPS there is even no 'Enable GPIO on EMIO Interface' option shown in the 'General' tab. And I tried your method to tick EMIO GPIO and set width to 1, there were errors popping up said I couldn't set a 64-bit bus with a width of 1.

Does it have anything to do with XPS license because I didn't purchase a license yet. Thank you so much!

aziz's picture
aziz
Junior(0)
UCF file

In step 31, the UCF file for BTNR.
NET processing_system7_0_GPIO_pin IOSTANDARD=LVCMOS25 | LOC=R18;

Did it suppose to have the word "_pin" there, because in the .v file it only have I/O for processing_system7_0_GPIO .

Then when I want to generate bitfile there is error:

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow

ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.

How to use the -g?

aziz's picture
aziz
Junior(0)
UCF file sloution

Add "[0]" at the NET name.

NET "processing_system7_0_GPIO[0]" IOSTANDARD=LVCMOS25 | LOC="R18";

fayyazrafiq's picture
fayyazrafiq
Junior(0)
UCF file solution

This is because of the LVCMOS25 because the master UCF file for Zedboard mention about the LVCMOS33. So change the IO standard from LVCMOS25 to LVCMOS33 will solve the problem.

umaair_653's picture
umaair_653
Junior(0)
UCF file sloution

It still doesn't works.
#Connect to Push Button "BTNU"
NET axi_gpio_0_GPIO_IO[0] IOSTANDARD=LVCMOS33 | LOC=T18;
#Connect to Push Button "BTNR"
NET "processing_system7_0_GPIO[0]" IOSTANDARD=LVCMOS33|LOC=R18;