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Zynqgeek Blog

The Avnet GitHub repository is the new location for getting access to all of your demo and
reference design needs! GitHub contains a historical record of all files and changes to
those files. GitHub is a social repository. This means you will not only be able to see old
and new changes to the repository, but you can actually subscribe to the repository to be
alerted when there are changes! Being a social method for developing, there are even
mechanisms for submitting changes BACK to the developers themselves!

This document is a list of suggestions as well as helpful information that will guide

Engineers working with Xilinx Zynq®‐7000 All Programmable SoC based solutions from

Avnet. Advice is provided for selecting and working with SD cards for their own system



SD Card Document here



If you want E book or hardback versions of the MicroZed chronicles you can get them below

Hello Zynq'ers!  This blog post will be walk you through a very basic (base) Zynq design using Vivado IP Integrator (IPI).  This post is the equivalent of the PlanAhead/EDK based flow blog post found here.  With the introduction of Vivado 2013.2, Zynq is fully supported within Vivado and IPI (definitely a game changer, and you are about to find out why).

Note: this tutorial was done on a i5 (laptop) with 8GB of ram running Windows 7 64 bit.

 Today, June 19th, 2013 Xilinx released version 2013.2 of their Vivado Design Suite. This release is particularly exciting because version 2013.2 adds to it Zynq support! YES!


A great question was posted by maw41 on the forums today:

maw41 wanted to know if he could pull the signals for the Ethernet MAC within the Processing System (PS) of the Zynq-7000 AP SoC device, out through the Programmable Logic (PL).  The answer is yes!

I thought I would take this opportunity though to talk about how to move signals from the MIO pins (those that are dedicated to the MIO Bank) to the EMIO pins (those that are available to the PL).


How to understand Zynq Pins! WooHoo!

A good question came up on the forums today by user atkarapa asking about MIO pins on the Zynq-7000.  So let's take a little bit of time going through what pins map to where, and get familiar with the naming schema that Xilinx uses for it's pins.

Last week Xilinx released the newest version of their tools, revisioned at 2012.3 (14.3).  I thought I would take a few minutes here to discuss a few things about Xilinx's tools, and how they are versioned.


Get to know the players

First let's get some nomenclature down:



ISE has been the primary Integrated Development Environment (IDE) for Xilinx for several years.  It is has been the primary launch point for all Real Time Logic (RTL) based projects